Delay a signal by a clock, or 2, or 3

[alank2]

I am thinking of messing around with connecting a Z80 to an AVR and using the AVR for the I/O.  A few people have done this using a 7474 flop flop to trigger the WAIT signal on the Z80 so the AVR can keep up.  On an OUT instruction from the Z80 this should be simple, AVR captures data pins and clears the flip flop to allow the Z80 to continue, but an IN instruction requires the AVR to put data on the bus, release the WAIT, but then it also has to get off the bus before someone else needs to use it.

This assumes that the Z80 and AVR and clocked synchronously...

Pseudocode for it might be:

isr_for_IN_to_Z80()
{
PORTx=data;
DDRx=0xff;
set_pin_to_clear_flipflop
DDRxX=0x00;
clear_pin_to_clear_flip_flop
}

So my question is, if the time between set_pin_to_clear_flipflop and the next instruction to set the port to input is too long (and I don't know if it is or isn't), what type of logic device would you use to delay the set_pin_to_clear_flop?  Something that could delay by 1, 2, 3, clocks, etc.

[JVR]

Simplest would be a decade counter, or a chain of flipflops.

[GeorgeOfTheJungle]

A serial in parallel out shift register, feed the signal into serial in, connect the clock, and tap it delayed at the parallel out pins, bit #n -> n clocks delayed.