strictly layout related
* in general, the board would look cooler if you use only 45 degree bends, you have some 90 degree bends
* maybe try moving the traces under the relays further away from the pads, there's plenty of room ( see REL_1 trace from top center pin to third pin from left)
* should't you be more consistent with those traces under the relays instead of placing some on top layer and some on bottom ( ex you have that Y shape of traces between REL_1 - REL_2 and REL_4 - REL_5 and then you do the same with REL_2 - REL_3 on the bottom ?)
* what's with the R22 .. r26 text on the bottom that's not visible on top .. weird
* consider align to grid or something like tht, to move those LOOP_x headers a tiny bit so that traces would be straight (from headers to relays)
* any reason for the \/\/\/\ with the trace on the bottom . you could keep that in a more straight line , stay above and under the relays and only dip down towards the pads and then back up
JRLY1 header / connector
* ... make the pads wider, doesn't seem any reason to be that thin.
* move that trace going from header to first relay up a bit so that it wouldn't go under the other connector's housing (just visual stuff, nothing wrong with it)
to the right
* C4 could be moved a bit lower to keep the traces straight.
* you could move c7 to the right of C8 or in better words flip them around . maybe rotate C7 so that square is above the IC pad it's supposed to go in , and rotate C8 so that the square pad is above its IC pad.
* what's the point of C6 there ... move it to the left of c4 , seems like plenty of room there, and you won't have a need to do vias this way
* you could probably also move R2 below VO1 so that you won't have a copper pour break between vo1 and r2 (the thermal relief shapes are messed up in your picture) and the trace cuts that ground pour on the bottom (if there's any pour) pointlessly, when you could place the resistor below the IC (or shift the MainOUT pad up since you won't have the trace there if you move C6 , and then put the R2 resistor to the left of VO1)
I'd move TRIM1 up a bit, and move C9 under it, and now there's room to move the 595 IC to the right and have all those traces more or less straight. the 90 degree bend on the trace from TRIM1 looks ugly
that long trace from m1 to r2 is kinda ugly but if it must be...
again, maybe you can make the pads of that IC slightly wider, they seem to be unnecessarily thin
to the right again .. any reason why the trace is thinner between R17 and R18 ?
If C5 is some decoupling capacitor for the MCP23017 IC, it really should be placed as close as possible to that pin, not all the way up there. move that voltage trace or whatever it is through the bottom of the chip but place the decoupling cap near the pin, not at the top.
* maybe remove the fill between the pins of jledpset, it looks pointless
* no reason not to use thicker traces between jledpset and mcp IC and maybe get rid of those orphan fills in the middle of the header
* same with the traces from mcp IC to the ULN IC on the right and then to the JRLY header there. it's small distance so it's not a current issue, but there's also no reason not to make them thicker.
* that copper pour between LR4 and LR3 is sketchy, i'd try to move the traces a bit and/or make them a bit thicker so that there won't be that orphan fill there.
maybe rotate U1 so that the bottom pin is at the top and then you don't have to move that trace like you do now .. and you'd have the three pads in a straight line on the bottom layer instead of having that Y shape
something weird with that trace going from the center pin directy into the copper fill ... shouldn't that pad have thermal relief then? worried you may have some mistake there.