Hi all,
I'm currently designing a high voltage amplifier for use with a piezo actuator. Electrically this actuator is equivilent to a 10uF capacitor. My design is based on the ADHV4702-1 evaluation board.
https://www.analog.com/media/en/technical-documentation/user-guides/eval-adhv4702-1cpz-ug-1444.pdf I've added a unity gain output stage to allow for a higher load current (0.1A). I've also added a shutdown feature such that when
SHUTDOWN_EN goes to 5V the amplifier is disabled and the output load discharges. For my appplication it is important the the output actuator can discharge/close in around 1ms during a shutdown event.
Any feedback on the topology/values would be much appreciated! My main concern is making sure that Vgs remains within 20V during shutdown - the 1M may be too large to allow the gate to discharge at the same rate as the output load, though the larger this value becomes the less the FET is contributing to the output current.
For reference the FET Q2 is a linear FET with a SOA that can handle 1A at 200V Vds (and 7A for 1ms). It has a input capacitance of 4nF (at 1MHz). The 39R discharge resistors can withstand 70W for 1ms.
Thanks!