Okay, made some very satisfying progress this evening. I got half of the scoreboard video segment decoder array soldered up onto the half-a-board of empty space remaining on the Vertical Timing board. This means that I can now generate a video display with player 1's score counter digits displaying on the scoreboard.
One thing that I was aware of and initially resigned to just living with is that because of inevitable and non-zero propagation delays through my horizontal ripple counter, the decoder circuitry and gate array, is that the generated digit segments would not all align 100% perfectly. Exactly how much of a visual impact this would have wasn't of course tested until now.
The first picture attached below shows the initial result. Well, not too bad at all and I guess a perfectly acceptable degree of quality for a display generated entirely with discrete transistors and diodes, right?
Well I stared at the screen for about 30 seconds and decided NO!. I suddenly remembered that I still had stashed under my bench the prototype discrete-transistor (again MPSH10) master-slave, pure-edge-triggered delay flip-flop (DFF) that I built as an evaluation piece for my 16-bit processor project. I described this DFF previously in reply #12 here:
https://www.eevblog.com/forum/projects/homebrew-digital-computer-system/msg460596/#msg460596 So, I switched off power and pulled the scoreboard video logic signal wire from the breadboard and wired it to the D-input of my DFF instead. I modified my clock oscillator buffer to provide complementary (out of phase) clock signals. One for the horizontal timing circuit ripple counter and the other exclusively for the clock input of my DFF. So now I have a DFF clocked half a period (1uS) out of phase with my video generator circuitry. This 1uS is ample time for all of my horizontal counting flip-flops to ripple-through and the decoding to settle. The Q output of my DFF is now the scoreboard video signal, delayed by half a clock cycle, rather than sent to the screen live. The DFF effectively operates as a memory cell/buffer. This is data deskewing, boys and girls.
The second attached picture shows the result - perfectly aligned digit segments. Yoo hoo! This project is slowly evolving into one of the more satisfying things I've built in a while. The third attached picture shows the complete set up as it currently sits. The circuitry on the bread board is just a couple of discrete N(AND) gates, a resistor matrix and a 75-ohm-zout emitter-follower buffer to combine the discrete logic-level video, blanking and sync signals into the one composite video signal.
As it currently stands, there are 107 individual transistors gating electrons. Considering what has been achieved so far for a video image, I don't think that is too bad at all
![Cheesy :D](https://www.eevblog.com/forum/Smileys/default/cheesy.gif)
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![](https://www.eevblog.com/forum/projects/oscilloscope-pong-for-1-or-2-players/?action=dlattach;attach=308488;image)
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