Oh and don't forget test points. I would put lots of those solder in eyelet test points all over the circuit to allow for easy testing of the blocks as well as use test points on most interblock connections so that one can see how the circuit works.
Yes, test hooks are planned.
For your trimmers, use vertical adjustable ones. This way, they don't need to be at the edge of the PCB, they can be easilly adjusted where ever you wish to position them. The vertical 10/25 turn trimmers also take less PCB space. Also, since you can't solder between the trimmer and top of the PCB, when wiring those, try to prioritize routing them on the bottom of the PCB.
All the main trimmers that adjust the geometry (stuff in the adjustment diagram) will be vertical ones, as they will be on the top board. There are a couple of other trimmers that control other stuff (like the reference voltage, etc.) and they will most likely be on the bottom board, so I've got two options there:
1) Use vertical trimmers and place a hole in the top board for an adjustment tool to fit through.
2) Use horizontal trimmers and locate them near the edge.
I don't think it's more than a couple of trimmers that will need to be on the bottom, so I may go with option 1 if I have enough space to include the holes. (I'll decide during layout.)
The reference trimmers will most likely be towards the edge of the board anyway, that's why I ended up specifying 15 turn horizontal cermet trimmers for that, but I can always change it during layout.
I think timb's current rendered layout is just for space approximation at this point. To generate a nice 2 layer PCB without spaghetti traces, potentially creating some oscillators due to trace length looping around in odd ways, he will be forced to optimally re-arrange the components in each function block when routing.
This. That's just how the components happened to group together when importing from the schematic. As you say, I will be forced to arrange things for optimal layout. This is due to a number of factors, including: Keeping trace lengths as short as possible, routing constraints on a two layer board, component pinouts, etc.