I'm building the buck converter from scratch for fun/learning and also because most off-the-shelf parts (except LTC3388) have very low efficiency at low loads.
Ah, okay. You will be well served to understand SMPS in the first place (it's not clear what your knowledge level is here), and then to optimize them for efficiency. A good lesson might be more of the methodology to optimize things. Measure subcircuits and see where the dominant losses are, and figure out ways to improve them locally. Then take a step back and see if you can swap around the functionality of those circuits, replacing whole sets with lower consumption types. Then repeat local optimization, etc.
A few years ago I did this exercise,
A switch and resettable fuse, with a bidirectional current limiting function.
For supply voltages up to 30V and currents up to 20A (selectable in 5A steps), this device will limit the current flow accordingly. The voltage drop is dissipated onboard, though it can be "recycled" through a ground pin, in which case it acts like a current-limiting buck converter.
This gives a sharper current limit than a dumb resistor, lower on-state losses, and a fast, no-wear fuse action.
It also has remote start/stop connections (via optoisolators), a one-shot timer (the fuse "blows" after 150ms), and thermal protection.
You can reset the "fuse" about ten times in a row, before temperature rises too high and the limit pulls in. Once it cools down a bit, you can continue to reset it.
One downside is, the onboard filter capacitors still draw some inrush current, and the filter inductor adds series inductance. Neither is a problem in the intended application -- switching loads with relatively large capacitances.
It's powered by a 9V battery, and boasts about a month continuous on time. I can't do that with regular off-the-shelf gate drivers, for instance: they all take upwards of 0.2mA Iq, as much as this circuit uses in total. And that leaves nothing for the current comparator, temperature sensor and UVLO. (On the upside, most do integrate UVLO.)
So the circuit is discrete, mostly BJTs, power MOSFETs of course, and a CD4000 gate.
The sense/drive circuit switches at up to 200kHz, with rise/fall time of 300ns or so, not terribly efficient but that fortunately doesn't matter in a device which is almost all loss anyway.
It actually consumes less power while active, as it steals some switching loss to power itself.
A purpose-made IC can absolutely beat the pants off this thing, easily 5x lower Iq I would expect. But no one makes one for this exact function, nor enough building blocks (comparators, logic, etc.) with adequate speed-accuracy-Iq tradeoff. So there's not much alternative.
And just a reminder that this is in fact a 600W power converter -- just not a terrifically purposeful one (it makes heat), nor for continuous operation. So, doing all that with good battery life, isn't too bad.
Yep -- I had the thought of doing something similar with two GPIO pins to deliver a turn-on/off pulse and a continuous keep-on current. That's still an option, but the power draw will need to be weighed against just using a few off-the-shelf level shifters (one 1.8V to 5V using a charge pump supply, then 5V to 12V).
There are better ways. They'll always take more parts, of course. Balanced configurations help a lot. You can have a circuit where transition current draw is relatively large, but quiescent current is low. This can be done at low current to begin with, and then sharpened with later stages (say, a CMOS gate). You can use a complementary emitter follower to drive larger MOSFET gates while wasting almost no current (the downside is 0.6V saturation to either rail; this makes logic-level FETs unattractive, but with a 12V supply, that's still perfectly fine).
For example, make a high-side "bus hold" latch: two CMOS inverters in a loop, with a resistor in series with each output so one or the other can be overdriven by a stronger load. Switch these with low side NMOS, driven from the MCU, complementary. There's your level shift, and it doesn't consume any Iq. Only 12V / R_series is drawn during switching, which can be say 100ns long. (The limiting factor is actually not so much the resistance, but the total charge of the opposite side gate's input capacitance plus the drain capacitance of the other NMOS. This can be some 10s of pF, which isn't terrible.)
Then boost up the output with a few inverters in parallel (this is fine using e.g. CD4069s, but be mindful when connecting Schmitt trigger gates in parallel (e.g. 74HC14), as their delays may not match, drawing extra shoot-through current), and drive whatever power transistor you need.
If you use NPNs instead of NMOS on the low side, you can add an emitter resistor, limiting the pull current; as long as R_series * Ic is enough to flip the "bus hold" latch state, it works. The difference is, this is true regardless of what the local ground voltage is: you could use 74HC14 or '04 here, and a bootstrap 3-5V supply, to drive an NMOS switch. (You wouldn't want to use strong NMOS to pull on a bootstrapped driver, because they'll want to pull it all the way to GND. Yes, you can add source degeneration all the same, it's just harder to calculate because Vgs(on) is higher and less consistent.) The bootstrap in turn might be supplied from a charge pump doubler from the 1.8V supply (or maybe you have 3-5V handy elsewhere, I don't know).
BTW, PMOS performs about 2.5 times worse than NMOS, so there is a real advantage, saving on Qg * Fsw current draw. Likewise, prefer a relatively small transistor (higher Rds(on), lower Qg(tot)), since conduction losses won't be your biggest problem here.
That's even an error that a lot of people make, even if they don't care about drive power: they see 4mΩ or whatever in the headline, and are sold on that. What could be better, right? Nevermind that the drain is 10nF at low bias, or the gate is 200nC. And then they get socked with all these losses, and their interaction with stray inductances, and the whole thing keeps blowing up...
There are also worse ways, that can still be alright in special cases. For example, a charge pump or DC restore circuit. You have a 1.8V swing on an MCU pin; capacitor-couple that to the high side, with a resistor bleeding off charge so it idles at +12V. Use something like RZM001P02, that only needs 1.8V drive. The catch: the 12V supply must not vary more than a fraction of a volt, or the cap will dutifully turn on (or erroneously turn off) the transistor. This makes startup and transient cases a bitch.
Yes, but if I calculate (from data sheet specs) that a given BJT would need, say, 500 nA base current to switch this load, can I actually use a resistor that high (for that example, 24M at 12V) or is there some other consideration that will prevent it from working consistently? Sort of like how pull-up resistors on open drain signals theoretically could be 1M, but at the cost of robustness (picking up noise that switches the input erroneously).
Note that BJTs are just as voltage-controlled as MOSFETs, so you still need to charge and discharge that base voltage. It's a lot less charge than a FET of the same dimensions, but you're at a disadvantage because you're doing it from 12V away. In short, 24M gives a long time constant (10s µs, if that?).
Typical solution is a B-E resistor to aid turn-off. (This also keeps collector leakage somewhat lower. Roughly speaking, C-B leakage flows into the base and gets multiplied by hFE. This is also roughly why Vcbo > Vceo: the leakage current contributes to a lower breakdown voltage.)
Is this one such part you're referring to? Just want to check because Linear tends to have good technical descriptions in their data sheets so I can research this further.
Like this, used one a bunch of years ago, still have the number handy:
https://www.analog.com/media/en/technical-documentation/data-sheets/3481fc.pdfNote the switch voltage drop is a fraction of what LT1074/6 does, because of the bootstrap. All the '74/6 can do is pull the base up to VCC, and the emitter hangs down by 0.7V or so per transistor. Supply goes down to 3.something V, whereas discrete MOSFETs aren't much use below 5-8V.
There are some old chips working in such a domain,
https://datasheets.maximintegrated.com/en/ds/MAX631-MAX633.pdf for example. (They're still available, amazingly enough, but are priced like an old boutique part. Not that they're exactly relevant, being boost type.) Voltage rating suggests metal-gate CMOS (ala CD4000, 74C00 family).
Note that the block diagram is much more than a comparator and driver, and these are still pretty basic devices.
At low currents, you'll probably be fine with hysteretic or PFM (or "pulse skipping") operation, but the peak current (and preferably the average as well) needs to be monitored to ensure safe operation.
You can use a few-us comparator, but that delay needs to be a small fraction of the total cycle, so you'll be in the low 10s kHz doing it that way, and you need
big inductors. This isn't a very cost-effective approach. But yeah, you can certainly develop an understanding this way.
Yes, but I didn't see a 12V input-capable one with very high ultra-low-load efficiency. I think that's because there's no real market for this kind of power optimization in 12V parts and thus no reason for semiconductor companies to invest R&D money in it. For ~5V, on the other hand, there's a huge market in portable devices and so TI and others have designed parts with incredibly low IQ (and thus high efficiency at low load), e.g. TPS7A02 LDO and TPS62840 buck (60 nA IQ).
A lot of regulators (of ordinary ratings, e.g. 30V input) boast low Iq, though it varies whether it's in shutdown or idle conditions. Can always wrap a hysteresis comparator around one, forcing burst-mode output while maintaining reasonable efficiency. Note that the comparator only needs to respond to voltage changes, i.e., 10s or even 100s of µs. The downside is a lot of output voltage ripple, but that's just going to happen in this domain, and again, you can LDO it, taking off only a fraction of a volt this time, to clean it up.
Tim
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