Can you explain more on why that is? I was definitely seeing that (the more displays I added to my bus, the more issues the *earlier* displays would have) but I don't quite get why. Is it just because the isn't any room for the signal to bounce back and conflict with itself?
Yes!
Consider the voltage on the transmission line.
The instant the transmitter transitions, it sends a current into the line. The current is set by the source termination resistor, and the line impedance. Let's say both are 100 ohms.
Thus, at the transmitter port, we have a voltage divider, say it's transitioning from 0 to 3.3V, then the pin voltage (assuming an ideal transmitter; it's not, but we can lump in its internal resistance with the source termination resistor, so this is fine) goes from 0 to 1.65V,
and that 1.65V wavefront propagates down the line.Some time later, a lone device at the far end, receives the 1.65V wavefront. The line is open (unterminated) at this end, so the wave reflects in phase, and at nearly full amplitude. At the end, the wave doubles up on itself and a clean 3.3V is received. Later, the wave returns to the source, adding its 1.65V level to the initial 1.65V level, setting the full line to 3.3V.
In effect, the transmitter tried to set the line to 3.3V, and at the speed of light (in the medium), that event is communicated over the length of the line. The transmitter must deliver current during this transition, to drive that event. It's not for free of course, there's energy stored in the line.
In practice, there is some loss and phase shift due to the transmission line itself, and the receiver pin capacitance. They act to round off the edge, or cause a little ringing. Likewise, the source end won't be perfectly terminated, so a little wave will reflect back off it, and so on and so forth; but as long as the double reflection is small (say, less than 20%), we aren't very interested in it. (Why 20%? This is about how much range a CMOS receiver considers a "valid" logic level.)
Now add a receiver midway along the line. What does it see? First nothing, then 1.65V, then 3.3V -- an indeterminate level is read for the duration of twice the distance to the far (unterminated) end. This perfectly describes the failure you observed, which is fortunate I guess, in that it failed exactly as one should expect!
Also, note that, if the line is longer than the pulse width being driven into it, then the transmitted and reflected wavefronts will both be in transit at the same time -- even stranger combinations (i.e. runt pulses) appear midway along the line.
If we load or double terminate the line instead, then the transmitter drives 3.3V into the line, and either 1.65V (source terminated) or 3.3V (unterminated) launches down the line, and at the far end, the wavefront is simply absorbed, leaving 1.65 or 3.3V along the line.
There is no double-time penalty for a reflected wave. Likewise, any receiver placed midway along the line, sees the same single wavefront -- and there is no problem with multiple wavefronts travelling on the line at the same time, so long as they're synchronized in time and direction.
Of course, for the double-terminated case, we need a receiver that can read a 1.65V threshold, likely not a plain old CMOS receiver.
And for the LVDS case, everything still applies, and we can ignore common mode propagation as long as everything is well behaved (but, be aware that it is still there, and will make you pay attention to it if you forget about it too much!). The differential signal is simply smaller (100s mV), and appropriate drivers and receivers are used to handle it.
(To a first degree approximation, differential pair PCB traces can be treated as individual transmission lines. So, you simply have whatever signal is travelling on each one, independently. Termination is one resistor per trace, and the differential termination is... simply the equivalent of both in series. We define common mode as the average voltage between the two lines, and differential as the difference. This is actually not a terrible approximation, on board -- not much coupling occurs between edge-adjacent traces. The coupling is more important in twisted pair cable for instance, and the calculations may change.)
Tim
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