This is more or less new to me. I know that there seems to be more supply rails than ICs on PCBs these days, and now I want to figure out how to sequence all these guys properly, or how other people do it.
1) In general is there some sort of algorithmic way to figure it out? So far all I've done is draw a tree to show the distribution from the main input to each rail.
2) Then there's the temporal relationship between the various rails.
In a mixed signal system, suppose there are some ADCs talking to a FPGA through some level translators. The ADCs need some analog VCCs and a digital VCC. There isn't any specific power-up diagram in the datasheet of the ADC I'm looking at but there are some interesting dependencies in the abs max ratings.
I don't even know what my question is anymore.
I mean I've looked at how other people do it (the sincerest form of flattery they call it), for example the 150-0320305-revd.pdf
www.linear.com/docs/45263anyhoo page 2. See the nice clouds on the left and the sequence on the right? I've got something twice as large to work on.
I have yet to see any CAD package address power sequencing the same way they address signal integrity or FPGA pin assignment. Is there such a thing, and if not, who wants to start a business with me?