Author Topic: OCXO frequency dividers and PLL multipliers  (Read 17427 times)

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Offline jpb

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Re: OCXO frequency dividers and PLL multipliers
« Reply #25 on: July 29, 2020, 09:34:35 am »
Forgot about that guy.

Are you referring to me? I always had the impression that canadians are polite and friendly. Well...
I think he was referring to the chip not a person - but perhaps you knew that, I'm sorry to take you literally if you were only joking.
 

Online BrianHG

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Re: OCXO frequency dividers and PLL multipliers
« Reply #26 on: July 29, 2020, 03:13:53 pm »
Forgot about that guy.

Are you referring to me? I always had the impression that canadians are polite and friendly. Well...
I think he was referring to the chip not a person - but perhaps you knew that, I'm sorry to take you literally if you were only joking.
Benta was playing with me.  Right after the line, I described the internal structure of the 74HCU04, it was understood when he deliberately erased that part of my answer in his quote of me.
 

Offline Benta

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Re: OCXO frequency dividers and PLL multipliers
« Reply #27 on: July 29, 2020, 05:14:50 pm »
@BrianHG: yes, I confess, I was winding you up a bit...  :)
 
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Offline Benta

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Re: OCXO frequency dividers and PLL multipliers
« Reply #28 on: July 31, 2020, 09:56:58 pm »
Played around a bit more with KiCAD and have a better feeling about it now.
But that's beside the point:

I now have the simplest divide-by-65 circuit for the OP.

Setting it up is simple using the equation 256 - N where N is the division ratio. In this case 256 - 65 = 191.

The counters are loaded with 191 (binary 10111111, but any division ratio can be selected using the Px inputs.

Cheers.

 

Offline Labrat101

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Re: OCXO frequency dividers and PLL multipliers
« Reply #29 on: July 31, 2020, 10:31:37 pm »
Hi I have a question
I have a very strong 3rd harmonic from my 50Mhz out from my PLL  3n502  which is multiplying by 2.5 from OCXO 20MHz
so the third @ 150Mhz should I try killing it with a filter will it smooth out some of the jitter.?
and if so how would I just kill this harmonic .
 The easy way if that's possible

 :popcorn:
RNS

 
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Offline Benta

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Re: OCXO frequency dividers and PLL multipliers
« Reply #30 on: July 31, 2020, 11:39:58 pm »
It's better to start your own thread for this.
 

Offline Johnny B Good

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Re: OCXO frequency dividers and PLL multipliers
« Reply #31 on: August 01, 2020, 12:42:55 am »
 That's entirely normal for a clock pulse output with nice fast clock edges. There's absolutely no need to add a filter which, in any case will either aggravate jitter or cause a complete clock pulse failure  elsewhere in the FPGA.

JBG
John
 
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Offline Labrat101

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Re: OCXO frequency dividers and PLL multipliers
« Reply #32 on: August 01, 2020, 08:50:49 am »
It's better to start your own thread for this.
WHY  . its within the scope of  ""  OCXO frequency dividers and PLL multipliers ""
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Offline Johnny B Good

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Re: OCXO frequency dividers and PLL multipliers
« Reply #33 on: August 13, 2020, 08:15:50 am »
One thing worth checking if that OCXO is a sine wave output type, is to verify whether it needs a 50 to 100 ohm loading to turn a soft sawtooth wave into an undistorted sine wave as I had to do with my CQE branded 12v 10MHz OCXO when I spotted a peculiar 2ns jitter on the falling edge of the square wave output of my 74HC14 sine to square wave converter/buffer circuit in the mark two build. How typical a requirement this might be for sine wave output OCXOs in general, I just don't know but if it can be a problem for one brand of OCXO, it's just possible it might also be a problem with other brands.

 I'll leave you to peruse those hand drawn circuit diagram sketches for now before turning this contribution into yet another monster missive. :)

JBG
I've always had noise issues with 74HC14.  74HC04 is generally near perfect.  74HC14 is generally good for cleaning up slow noisy transition signals below 1MHz where jitter is not a critical factor.

 Sorry for the delayed reply, Brian.

 I was reviewing these posts and realised I should have responded to this one. Better late than never and to set the record straight, here's what I'd have said at the time.

 I don't doubt that the 74HC04 may have been a better choice in this case but I just went with what I had (and I now have a rather large collection of HC14s to burn through  :) ) but in this case, the peculiar 2ns jitter on the falling edge (triggering the 'scope on the rising edge) was entirely down to the distorted sine wave from the OCXO.

 After trying other component changes, I eventually cured the distortion using a 100 ohm resistor directly across the OCXO's output before the 1nF coupling cap and the 1K series resistor (now a 160 ohm resistor - which, as it turned out, was not a critical change) going to the 'HC14's input pin.

 As it happens, getting the 'mid point' bias adjustment just right is critical to nulling out 2nd order harmonics (the lpf does a better job when it only has to deal with odd harmonics starting at 30MHz rather than also having to deal with even harmonics starting at 20MHz).

 In hindsight, I should have padded that 5K trimpot with a couple of 2k2 resistors to make the adjustment more stable and easier to achieve. I'd had to readjust it again a few days later which need had me worried that perhaps it wouldn't remain stable for very long. However, it seems to be stable enough since that final adjustment but I'll keep the padding option in mind for any similar 'bias trimming circuits' I might need in future projects.

JBG
John
 

Offline Labrat101

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Re: OCXO frequency dividers and PLL multipliers
« Reply #34 on: August 16, 2020, 04:40:51 pm »
Hi Bad_Driver & JBG

 Things seem to have gone very quite.  I am very much going to buy the UTG962 Function Signal Generator
 I know that the Square wave rise time is a bit slower than the FY68 .. But it works out the box .
And all the time and effort I have put into this . its showing sign of failure the Jitter is not stable any more
the sine has started to show weird rounding at the top.  I should have some how binned it when the PSU
went up in smoke after an hour of use .
 The Specs on the UNI-T are good and they do have after sales support .. some what.
 And it has some really nice features that are really missing on the FY...
 I read the manual from UNI website.
 it has really a lot more functions and a real sync output for scope this is a plus .
 And even in this forum I can't find any one who has said anything bad about it.
 
 Still waiting for my Leo Bodnar GPSDO to turn up .
  How was London?   8)

Have fun stay safe
 :popcorn:

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Offline Bad_DriverTopic starter

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Re: OCXO frequency dividers and PLL multipliers
« Reply #35 on: August 19, 2020, 11:30:21 am »
Hi Friends,

sorry, unfortunately I was not available during the last weeks since I was in London (really strange during Covid-19!!!) and got some housekeeping problems at home with my water tubes.
So there was no free time beside my family and my job for sitting on my desk  :-//

Independent form Brena I came to the same solution with the divide-by-65 counter (load the value =256-65 into the registers of a 8 bit counter). In my simulation it seems that the first
suggested schematics of Brena doesn't work but may be I made an error.

After finding some working solutions I came to the KISS conclusion . Keep it simple and short. The 65 MHz OCXO can rest for further investigations a while.
So I found two cheap Trimble 34310-T 10 MHz OCXO in China and I'm hoping that they are on a fast boat to Europe  :-DD

During my vacation I read a lot about frequency, time, noise/Jitter and I got the feeling to become a time-nut  :palm: but why not? I got the strong feeling that
I need a very good counter or a new device for further improvements  :box:

Because there was only little time I have found only 2 hours for the following experiment (may be useful for our GPS friends) to get a feeling on GPS accuracy. 
 
I checked the 1 pps pulse of my 4 GPS receivers again each other in a simple setup. You can see (or better believe that they are there) all 3 Neo n6m and my Neo m8n on the bread board.
The n6m's are connected to local ceramic antennas nearby (not perfect) but the n8m has an external antenna on the roof (3m away).

Thanks to my SDS2000X Plus I measured the pulses for more than an hour.  You can see the statistics in the screen shot. Track 1 (yellow) is from Neo m8n.
15...20 ns may be caused by the distance of the roof antenna to my breadboard. The other neo's may be  suffer from reflection and bad signals on my bench.

I ordered 3 new external GPS antennas and will repeat the experiment asap. I keep you informed!

Johnny, I found an information that it's possible to read out from the UBlox Neos helpfull informations regarding the absolut error that can be used for corrections.
You need an Andruino setup for that.
« Last Edit: August 19, 2020, 12:07:03 pm by Bad_Driver »
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Offline Benta

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Re: OCXO frequency dividers and PLL multipliers
« Reply #36 on: August 19, 2020, 03:22:30 pm »

Independent form Brena I came to the same solution with the divide-by-65 counter (load the value =256-65 into the registers of a 8 bit counter). In my simulation it seems that the first
suggested schematics of Brena doesn't work but may be I made an error.


My apologies! In the meantime I've done an exact timing analysis of the programmable counter using 74AC161. It will only operate at up to around 35 MHz.
Sorry for wasting your time :(


 

Offline Benta

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Re: OCXO frequency dividers and PLL multipliers
« Reply #37 on: August 19, 2020, 04:26:15 pm »
Actually, the ideal solution would be the ON/NXP prescalers MC12034, MC12052, MC12053, MC12054 that are in SIOC-8 and capable of dividing by 64/65.
Downside: they're all obsolete.

 

Offline Labrat101

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Re: OCXO frequency dividers and PLL multipliers
« Reply #38 on: August 19, 2020, 06:45:54 pm »
Quote
Thanks to my SDS2000X Plus I measured the pulses for more than an hour.  You can see the statistics in the screen shot. Track 1 (yellow) is from Neo m8n.
15...20 ns may be caused by the distance of the roof antenna to my breadboard. The other neo's may be  suffer from reflection and bad signals on my bench.
Hi . I might be wrong but if you are using all 4 channels on your scope there will be a slight difference due to the way the scope
divides the triggers (shares) the trigger levels .
Try to use the alternative mode where you can set the trigger reference to each channel independently .
you will find that c4 will be nearer to the others .

Also did you read my post a few up . There is a Bug in the cyclone chip its self and its not the software .
 The input of the cyclone chip is failing on the xtal input . as per the manual the chip has an internal counter that's meant to control the
 internal DACs  stability and I think (know) these are NOT originals and putting a fast rise pulse instead of the cheap xtal that they used with a slower rise time was also just on the max .
The cyclone can be run with a 100mhz xtal on the other pin .. (forgot the number off hand) .
You can see the distortion from the pins going to the dac inputs  Left & right of the cyclone .
The jitter is caused but the second internal timing dac being out of phase by 1.5deg . this was on my chip and varies  as much as 5deg.
 so there are 2 pulse overlaying It is also visible on the sine as well but harder to see as the rising edge of a sine is much slower than
 A square or pulse . So it appears to be jitter but its not because I can see it as low as 2mhz . its hard to see as its within the width
of the scope line . Set the scope to Dots and Persistence 1s  all becomes clear.
 
This maybe just on my FY68 and I got the Big Lemon instead of a small Lemon.   |O


If your interested I found that Ali Express is shipping supper fast I order some stuff and it has arrive within 
8 days (working)  I could not believe how fast.

 My Uni-T UTG962 should be here next week  .. I have had it with FY . and I was not going to chance there BS Data sheet again.

 I might do a comparison .. but I have a feeling it will be like comparing a  :horse:    :popcorn:  :-+

Update attached photo of the overlay that comes ns after . ..
    if its not an echo that would mean the jitter is negative in time .. and so far, that's not possible yet
The dots are a tracer that I put to show the neg pulse
 The second trace is appearing a few ns after the first trace out of phase . giving the appearance that's it a negative
 This also visible from the cyclone output pins .

Have Fun
 :popcorn:
« Last Edit: August 19, 2020, 08:57:58 pm by Labrat101 »
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Offline Bad_DriverTopic starter

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Re: OCXO frequency dividers and PLL multipliers
« Reply #39 on: August 20, 2020, 08:27:06 am »
Sorry Benta for misspelling you nickname  |O
As I learned with this synchronous counter simulations it seems that the reset or load pulses are to short or coming to late for the first counter stage.

Attached my (in the simulation) working by-65-divider with 74XX161, unfortunately I found only the 74AS161 in the database (not the AC), therefor I'm not sure that it will work at 65 MHz. (sim only with 26 MHz)

My first described 65 MHz by-5 solution worked only by accident - I forgot in my first design the connection to the first flip/flop, the "original" Johnson counter
didn't work  :palm:
« Last Edit: August 20, 2020, 08:59:08 am by Bad_Driver »
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Offline Bad_DriverTopic starter

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Re: OCXO frequency dividers and PLL multipliers
« Reply #40 on: August 20, 2020, 11:01:07 am »
Hi Labrat,

hope you are doing well!

You are wrong with your assumption regarding the 4-channel-setup. Attached you find a screen shot with the same setting but with all 4 channels connected to the output of the Neo m8n.

Yes there can be a slight difference between channels (what can be fixed with the skew settings) but these are measured in ps and not the ns as you can see. (1ns = 20 cm)
Because I own a Leo Bodnar-pulser I will do this skew testings later and will show the results (yes, it's the Leo Bodnar you ordered the GPSDO from), the pulse from the Neo is not sharp enough.

Regarding the Feeltec stuff it's really a pity. But I learned a lot from that improvement experiment and my FY works for me with all the little weaknesses.
And now the (not VC)OCXO drifts into the right ballpark  ;)

And I learned that I will not do the same mistake twice. It's better to spend more money than to jump to short. I'm happy with my SDG2042 (now 2122)
I hope you will become happy with your new purchase!

I'm keeping looking around for a HP 53131A but at EBay they are to expensive for me (or are located oversea with risky TAX issues) and it's hard to find
a device here in Germany.

If I find the time I come back with a PM.

regards V
« Last Edit: August 20, 2020, 11:02:51 am by Bad_Driver »
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Offline Labrat101

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Re: OCXO frequency dividers and PLL multipliers
« Reply #41 on: August 20, 2020, 01:16:54 pm »
Hi. I did say I might be wrong .
 I forgot you had the pulser.
 sorry I missed the ps    :palm:   had to much  :popcorn: & Beer :-+

I am still waiting for my goodies to arrive . Looking on worst case scenario.  It can't be any worse.than a FY.
 
« Last Edit: August 20, 2020, 01:39:06 pm by Labrat101 »
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Offline Benta

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Re: OCXO frequency dividers and PLL multipliers
« Reply #42 on: August 20, 2020, 05:10:23 pm »
Sorry Benta for misspelling you nickname  |O
As I learned with this synchronous counter simulations it seems that the reset or load pulses are to short or coming to late for the first counter stage.

Attached my (in the simulation) working by-65-divider with 74XX161, unfortunately I found only the 74AS161 in the database (not the AC), therefor I'm not sure that it will work at 65 MHz. (sim only with 26 MHz)

Unfortunately it won't be much faster than the 74AC161 version, perhaps 40 MHz.
Correction: the 74AS161 will actually be slower than the 74AC161.



« Last Edit: August 20, 2020, 06:47:17 pm by Benta »
 

Offline Bad_DriverTopic starter

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Re: OCXO frequency dividers and PLL multipliers
« Reply #43 on: August 20, 2020, 05:28:35 pm »
Yes I think any asynchronous counter with reset or set logic will be to slow.

My Johnson counter solution only works because of my mistake with "forgetting" the reset-connection to the first stage.
Later I connected it to Vcc. But a lot of great invention were done by accident  :-DD
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Offline cdev

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Re: OCXO frequency dividers and PLL multipliers
« Reply #44 on: August 20, 2020, 11:40:09 pm »
You guys have got to see the homebuilt GPS-timekeeping device one of the users here uploaded pics of a couple of years ago, it was just totally over the top. And it worked. It llooked like something out of Doctor Who. 

This guy could have made a living designing one-of-a-kind art like that.

I vaguely remember that his GPS used a handmade quadrifilar helix antenna sticking out of its top. :)  Search for it, its worth looking for.


Well done I glade you got it . Finely figured out .
I just love your breadboard.  you can sell that as an  Art master piece .  :-+

  :popcorn:
RNS

 
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Offline Bad_DriverTopic starter

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Re: OCXO frequency dividers and PLL multipliers
« Reply #45 on: August 21, 2020, 10:01:23 am »
I belief  this unseen. There a thousands of posts reagarding GPS time solutions. At the end you catch the atomic standards with your efforts  :-DD

Yesterday I found a cool well thought solution and I couldn't hesitate to buy it.

Unfortunately only in german
http://dl0wh.de/wp-content/uploads/2015/02/DF4IAH-10MHzRefOsc_V2_UKW60-Skriptum_20150901.pdf
but there is a english GitHub source
https://github.com/DF4IAH/avr_DF4IAH_10MHz_Reference

I'm not sure if the source of all the chinese GPSDO's is this project.

And I love what is possible with my new Siglent SDS2000X+, another run with my GPS-receivers.
You can see very well the gausian distribution of the time differences between the triggered Neo m8n und the 3 Neo m6n.
Display persisting infinit. Run abaut 4h.
« Last Edit: August 21, 2020, 10:57:08 am by Bad_Driver »
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Offline Benta

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Re: OCXO frequency dividers and PLL multipliers
« Reply #46 on: August 21, 2020, 08:01:47 pm »
@Bad_Driver, I think I might have solved your issue.

Remember that I mentioned some obsolete Motorola/ON Semi parts?

Well, it turns out that a company in Arizona is still making them. Lansdale Semiconductor seems to have specialized in obsolete RF parts and is producing them using a foundry.

Here's your part, SO-8, divide-by-65 (and 64, 128, 129). You'll probably need to level shift its output. Don't pay attention to the minimum input frequency, that's only an issue with sine-wave input; if you provide a square-wave it'll work fine. Otherwise ML12017 is an option.

http://www.lansdale.com/datasheets/ml12052_reva.pdf

Cheers  :)
« Last Edit: August 21, 2020, 08:16:33 pm by Benta »
 

Offline cdev

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Re: OCXO frequency dividers and PLL multipliers
« Reply #47 on: August 23, 2020, 01:02:09 pm »
Wenzel also has written on diode frequency doublers.

Very easy to make.

Also, TVB has made his PicPets and PicDivs as well as source for them at

http://www.leapsecond.com/pic/

made from PIC microprocessors so verifiably accurate and inexpensive.

Have you looked at this Wenzel paper:
http://www.wenzel.com/wp-content/uploads/dividers.pdf
You can increase the effective frequency of dividers by adding analogue circuit bits (to put it crudely).

Look at the section : Getting More Speed from a Logic Family
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Offline Bad_DriverTopic starter

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Re: OCXO frequency dividers and PLL multipliers
« Reply #48 on: August 24, 2020, 07:10:24 am »
Thanks Benta for the link, seems an interesting business to provide military facilities with genuin new old parts! I went trough the websites - worth reading!

@ CDEV:
I know that diode frequency doubling is used in RF for decades, it was for a long time the only way to do that (before we got PLL and synthesizers).

But the hint with the simple PICs is interesting! Much easier than programming Arduino or Raspi. (and I wish to have 3 cesium clocks to drive into the hills  :=\ and prove Einstein - follow CDEVs link)

I think I give it a try. Programmers are available for about 12 € and the PICs for about 1€/p.
And with some shaking of my brain my old assembler programming capabilities will show up again  :-/O

But I run short of time for hobby these days  :phew: will take a while.
« Last Edit: August 24, 2020, 08:59:06 am by Bad_Driver »
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Offline cdev

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Re: OCXO frequency dividers and PLL multipliers
« Reply #49 on: August 26, 2020, 12:41:26 am »
Thanks Benta for the link, seems an interesting business to provide military facilities with genuin new old parts! I went trough the websites - worth reading!

@ CDEV:
I know that diode frequency doubling is used in RF for decades, it was for a long time the only way to do that (before we got PLL and synthesizers).

But the hint with the simple PICs is interesting! Much easier than programming Arduino or Raspi. (and I wish to have 3 cesium clocks to drive into the hills  :=\ and prove Einstein - follow CDEVs link)

I think I give it a try. Programmers are available for about 12 € and the PICs for about 1€/p.
And with some shaking of my brain my old assembler programming capabilities will show up again  :-/O

But I run short of time for hobby these days  :phew: will take a while.

I am not a programmer and am the kind of guy who prefers not to reinvent the wheel if I can avoid it, that said, I really want to learn how to program PICs because TVB's code does look accessible, he's annotated it well, and it just looks SO very useful.

So, I bought a bunch of 12F675s and they are sitting right here, I will probably burn two of them within the next couple of days to help me with my build of LARS's GPSDO which I am just beginning. A picpet and a GPSDO paired up makes a VERY good, but also very affordable timer.
« Last Edit: August 26, 2020, 12:52:07 am by cdev »
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