After going of topic in other boards I follow the suggestion and open a new board.
It should be used for discussions around unusal frequency dividing schematics needed
to reach useful frequencies for PLL synch with GPS time bases as example.
In my case I try this with an 65 MHz OCXO and some NOS schottky Flip-Flops. Since I‘m not
an expert but doing this as hobbyist I hope for hints and examples from others.
Well, becoming an "expert" is essentially down to gathering plenty of "experience".
Do enough 'experimental' solderless breadboard builds and you'll become an "expert" soon enough!
Still and all, there's no harm in reading up on other experts' experience to better prepare yourself in trying out various ideas and avoiding the pitfalls in breadboarding such circuits whether on solderless or vero(strip) boards (or even deadbug style on copper clad board layouts).
Since, despite being "off topic", those circuit drawings I'd attached in the SDS2000X+ topic thread had attracted sufficient enough interest to be viewed 94 and 78 times to date, I've decided to attach them here for easy reference.
The first shows the circuit for the mark one with its 13MHz OCXO and all the TTL jiggery pokery required to turn it into a 10MHz reference. I don't think adding U1 helped very much, if at all since the 3n502 clock multiplier doesn't require a perfect square wave input clock to provide an ultra low jitter (20ps pk-pk) square wave output.
As for dividing the OCXO's output down to 32.5MHz, I wasn't sure whether 74S74s actually existed but I tracked down an entry for one in my TI TTL data book (75MHz min, 110MHz typ clock inputs speed). If you find an equivalent to this in your collection, you're in with a chance (provided you can select a 74193 that's fast enough for the job).
If you can find a 74S169 or equivalent, you can use this to divide by 13 straight from the 65MHz input (count up clock input speed is given as 70MHz typical). the '169 isn't identical in function to the '193 (it uses a single up/down control input and a ripple carry output with T and P enables versus separate clock inputs to determine count direction and borrow out/in and carry out/in connections of the '193). Both are programmable input synchronous counters but whether this means the '169 can also be used for modulo N counting isn't too clear from the notes.
On the other hand, you can probably find a modern multipurpose programmable divider (PIC?) to do this with a single 8 pin chip (assuming you can find one that can deal with a 65MHz clock input). In my case, I was lucky enough to be dealing with a low enough starting frequency (26MHz) to drive the clock input on my selected 74193 making it easier for me to do what you're proposing to do with your own collection of ancient TTL.
One thing worth checking if that OCXO is a sine wave output type, is to verify whether it needs a 50 to 100 ohm loading to turn a soft sawtooth wave into an undistorted sine wave as I had to do with my CQE branded 12v 10MHz OCXO when I spotted a peculiar 2ns jitter on the falling edge of the square wave output of my 74HC14 sine to square wave converter/buffer circuit in the mark two build. How typical a requirement this might be for sine wave output OCXOs in general, I just don't know but if it can be a problem for one brand of OCXO, it's just possible it might also be a problem with other brands.
I'll leave you to peruse those hand drawn circuit diagram sketches for now before turning this contribution into yet another monster missive.
JBG
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