Noise on Power Rail Due to MCU Sleep

[colorado.rob]

I'm seeing this on my 3V3 power rail on a mixed analog/digital system.



These 8mV changes in output correspond to work/sleep cycles in the MCU.  I don't have a separate VDDA rail and suspect that this is affecting the performance of the ADC since it pulls VREF+ from VDD.  According the the datasheet this equates to 3LSB.

The image is actually pretty interesting since it not only shows the work cycle of my signal processor on the power supply rail, but also the FreeRTOS tick counter.  In fact, I find it rather surprising that it is even visible at all given the other sources of intermittent current draw in the system.  And there is only a maximum difference of 6mA difference between sleep and run mode.  Why is this so visible in the power rail?  There should be plenty of bulk capacitance (4.7uF) on that rail and every VDD pin is well bypassed.  Total power draw averages just 22mA @ 3.3V.

Is there something I am missing or should be concerned about with this?

I think I can just scale the MCU speed down so that the sleep times are non-existant by 48MHz rather than 80MHz to eliminate this.  It's probably more efficient that way.

The questionI guess I have for you all is whether it normal to see such a impact on VDD from MCU activity or does it point to a potentially bigger issue I should be concerned about?

[David Hess]

It looks normal to me.

The regulator has a finite output resistance do to limited open loop gain and series resistance between its feedback point and the load.  This produces those large steps which could be decreased if necessary to practically zero by using remote sense and more open loop gain like from an operational amplifier.

It is not real clear how wide the spikes from the tick counter are but both the ESR and ESL of the decoupling capacitors limit their effectiveness.  Controlling that would require better decoupling and likely a better layout.

Probing this level of noise is not trivial with a standard oscilloscope probe.  As a test, connect the probe tip to ground where the ground lead is attached.  You will likely still see something indicating that a differential probe will be necessary for a more accurate measurement.

One thing that might help with the ADC reference is to separately decouple it directly to its ground and add a separate reference using that same ground so as ground gets pulled up and down, the reference input does also.  This would be separate from removing noise from the ADC inputs however.

[danadak]

Sure seems like bypassing at issue. Right at processor pins, Vdd to Vss, should
be a bulk cap, like a polymer tant, and a ceramic disk, .01 to .1 uF. Look at cap
datasheets, not all caps of same value exhibit good esr.

Take a look at LM317 response in datasheet. I looked at 78LXX series, in the
two datasheets I looked at no transient response info.


Regards, Dana.

[David Hess]

Sure seems like bypassing at issue. Right at processor pins, Vdd to Vss, should
be a bulk cap, like a polymer tant, and a ceramic disk, .01 to .1 uF. Look at cap
datasheets, not all caps of same value exhibit good esr.

As shown, the settling time is too fast for this to be a decoupling problem except maybe for the timer spikes but we cannot see enough detail to really know.

Take a look at LM317 response in datasheet. I looked at 78LXX series, in the
two datasheets I looked at no transient response info.

Load transient response time for an LM317 or 78xx regulator is 10s of microseconds at most.  (1) The Siglent as configured is taking a sample every 1 microseconds so it is definitely picking it up however I do not know how it is processing 14 kpoints down to the display resolution of 20 microseconds/point.  If the transient response is visible, it should be only 1 or 2 pixels wide.  I marked up the image to show where the effect of the decoupling should be visible and it looks fine.

The 8 millivolts of shift is from the output resistance of the regulator and series resistance between the regulator and load.

(1) From Fairchild Linear Integrated Circuits Databook, 1976.  It was just the closest source that I had handy.

[Kleinstein]

With many regulators the output resistance can be relatively high at light loads. The voltage drop of 8 mV at 6 mA change suggests something a little over 1 Ohms. The transient part should be rather fast and thus looks good here. So no visible problem with decoupling.

One cold try a different voltage regulator - not all are the same with respect to output impedance.

Reducing the clock and this way reduce the sleep time could be an option - with an average of 22 mA saving a few mA for a few 10% of the time might not be worth the trouble of using a sleep mode. Going down in clock to slightly more than half (e.g. 48 MHz) would also reduce the CPU current so it would be only some 4 mA to save for maybe 20% of the time - thus less than 1 mA overall - this might be less than the power consumption of a regulator with much better regulation.

Another option might be changing the code, so that the critical part is not to short after going out of sleep mode. With a low capacitance this could be enough to have the voltage settled to the lower value. Just avoid using the ADC in the transition time. Both ways of more or less filtering caps could be a solution - though more filtering could be tricky due to the extra OS pulse.

[fcb]

Check that your not actually seeing noise in the 0V caused by your layout, and /or parth back through the scope ground.

Robustify/isolate your ADC reference etc...  Publish a schematic.

[David Hess]

One cold try a different voltage regulator - not all are the same with respect to output impedance.

With many regulators the output resistance can be relatively high at light loads. The voltage drop of 8 mV at 6 mA change suggests something a little over 1 Ohms. ...

What I have done in the past, if I did not use separate analog and digital grounds which is preferred, is either add an operational amplifier to implement remote sense or build a discrete regulator with remote sense using an operational amplifier, pass element, and reference.  The later can achieve microohms of output resistance at the sense point.

[floobydust]

OP why did you not filter AVDD? Worst thing you can do for A/D performance, next to bad grounding.
Consider using an RC or LC filter from VDD to AVDD.
Like 47R or 10uH makes a huge difference, and the few mV of PSU noise becomes irrelevant.

[colorado.rob]

Hi folks,

I really appreciate everyone's feedback.

This issue of resistance between the MCU and LDO is the key here. I am using a 1? analog switch (DG4157) to switch between LDOs (one for run mode, one for standby) in order to save some board space, reduce BOM cost and save a little time.  The DG4157 can easily handle the 50mA max current.  But the 1? on resistance is causing this issue.  The analog switch is there to eliminate the reverse current through the unused LDO. It also has a really fast switch time, so I don't need to worry about load switch timing.

The AVDD is filtered via a ferrite and a couple of capacitors.  But these filters are not designed to eliminate such low-frequency noise.  A 300Hz signal is really hard to eliminate.  At 47?, you'd need 150uF to reduce the ripple by half.

I have a few options to fix this:
1. go back to a few discrete mosfets to switch between the two LDOs (MIC2211 and MCP1700 for the curious).  I can get down to under 0.2? I think.
2. remove AVDD from the analog switched MCU power rail.  I can pull it directly from the MIC2211, which is switched off during standby.  This is probably the "A" option for me.
3. without changing the board, I can lower the ripple by reducing the MCU speed from 80MHz to 48MHz and never sleep.  This requires no change to the board at all.  There is only about 3mV ripple in this case.  Power consumption is slightly improved.

Does anyone have any smart ideas for powering an MCU during standby?  I need to retain SRAM (or put in an EEPROM and just shut down).  The MCP1700 had a pretty low quiescent current (1.6µA) but really shitty step response and PSRR.  The MIC2211 is nice and quiet but has a higher quiescent current than I can afford during standby. I'm using an STM32L4 which requires between 2-3.6V.

[David Hess]

So if you had a micropower regulator with good step response and PSRR, you could use that?

Why do you need such a high PSRR?

How low does your quiescent current need to be?  As low as possible?

I thought maybe you were running the microcontroller on minimum voltage during shutdown and higher voltage while operating to save power.  This works but at the cost of complexity.

A part like an LT1120A seems ideal because it has a reference output and with some cleverness you can switch the regulated output voltage but I don't know what its step response is.