N-Chan MOSFET Switch: Does Reqd VGS Charge For Turn On Increase With IDS?

[mbennett555]

I recently built a simple latching switch for a DC load, using an N-channel MOSFET.  The MOSFET is an On Semiconductor FQP19N20C.  The circuit diagram is attached here.

As shown in the circuit diagram, there is a capacitor set, with capacitance C= 300 uF, that provides the VGS voltage to the MOSFET to put the MOSFET in State= On.  To charge the capacitor set, the user pushes a momentary switch for t>= 1 s.  Right after the user releases the switch, the value of VGS is 22 V. 

As shown in the circuit diagram, in order to monitor VGS with an oscilloscope, I connect a scope probe to the output of an OPA (operational amplifier) buffer, which is shown in the diagram.  Of course, if I didn't do this, the impedance of the scope probe would affect VGS.

1) First, I disconnected the DC load from the MOSFET switch; so even when the MOSFET is in State= On, IDS= 0 A.  I used a digital scope to look at VGS, right after I push the momentary switch to charge the capacitor set in order to put the MOSFET in State= On.  With the scope's time scale set to 2 ms/div, I see that VGS looks like it increases linearly.  Of course, it's not actually linear, it's exponential; but at that time scale, it looks linear.  And there are no "glitches" in the VGS waveform.

2) I then connected a resistive DC load to the MOSFET switch, so that the final value of IDS (after about 2 s), is  3 A; when the MOSFET is in State= On.  I again used a digital scope to look at VGS right after I push the momentary switch to charge the capacitor set in order to put the MOSFET in State= On.  I consistently see that, about 3 ms after the switch closes, and when VGS~ 5 V:  VGS temporarily drops to VGS= 0 V for about 1.6 ms.  VGS then goes to VGS~ 5 V, and continues to increase, to its final value of VGS~ 22 V.

Shown below are 2 screen captures from the scope.  For each one, the channels are: 
•   Ch1 (Color= Wht).  IDS.  (The vertical scale is labeled 2.00 V/div, but the true units are 2.00 A/div.)
•   Ch2 (Color= Grn).  VGS.
•   Ch3 (Color= Ylw).  VDS.
•   Ch4 (Color= Blu).  22 VDC bus for VGS.

Screen 1.  The image below shows the screen capture for the case:  DC Load= 0 A.  We can see:  1) The green waveform, VGS, has no glitch in it.  2) The blue waveform, 22 VDC bus, has a constant value.



Screen 2.  The image below shows the screen capture for the case:  DC Load= 3 A.  We can see:  1) The green waveform, VGS, has a glitch, because at VGS~ 5 V, the voltage changes so that VGS~ 0 V for about 1.6 ms.  2) At the same time as the glitch in the green waveform, the blue waveform, 22 VDC bus, drops from ~22 V to ~19 V.



The data sheet of the On Semiconductor FQP19N20C MOSFET is attached here.  On page 3, we can see that the typical value of "Total Gate Charge", when IDS= 19 A, is just 40.5 nC (nanoCoulomb).  If I use 2 of the values stated above (C= 300 uF for the capacitor set connected to VGS; and at VGS~ 5 V, VGS goes to 0 V temporarily); and the equation Q= CV, where Q is charge, C is capacitance, and V is voltage:  I calculate that when the capacitor set has a voltage VGS= 5 V, its charge is (300u)(5)= 1.5 mC (milliCoulomb). 

My question is:  Why does the MOSFET switch need to get 1.5 mC of charge from the capacitor set when a load is connected to it; but if no load is connected to the MOSFET switch, the MOSFET doesn't need to get any charge from capacitor set (ie, there is no visible "glitch" in the VGS waveform)?

Please note that, as shown in the circuit diagram, there is another capacitor set, with C= 200 uF, connected to the 22 VDC bus that provides the voltage for VGS.

[HiZ]

From the second scope image you've attached, I suppose the 22V rail is derived from de 120V rail that is on the high side of the load. I assume this because that brief 12A spike made the 22V rail tank along with the 120V rail.

The PSU probably isn't able to cope spike - or at least, isn't very happy - with that 12A spike, so C302 and C202 are doing their jobs as decoupling capacitors. If the capacitance of C302 is smaller in comparison with C202 (which is in parallel with VGS and the gate capacitance, which is negligible) and the resistance R102 is small, C302 will be discharged sooner, introducing that glitch you see with the load turned on. That explains why there is no glitch without the load: the PSU voltage doesn't tank and the decoupling capacitors C302 and C202 stay charged.

[David Hess]

Vgs does not change, however the gate charge required to turn on or off increases by a lot when the Vds changes because of charged pumped through the reverse transfer capacitance.  The amount of charge is so great that at high voltages, the reverse transfer capacitance dominates the input capacitance despite being several times smaller.

[mbennett555]

Actually the 120 VDC comes from a separate DC power supply, as shown in the circuit diagram. 

IMO you brought up an excellent point.  Each DC power supply (there are 2) is plugged into the same AC outlet.  The AC voltage at that outlet may drop enough, during the few milliseconds when the current supplied to the DC load spikes to ~12 A, to cause the DC power supply that provides 22 VDC to sag that voltage to ~19 VDC.

Thank you.

[mag_therm]

I think David has identified problem.
The 300 uF is holding the Vgs in the active zone during turn on and turn off.
If this is permanent circuit, one suggestion would be to delete the 300uF completely,  use a driver that can source and sink the peak 220 mA.
Use a debounce for both switches to control the driver.
Gate capacitance is around 1500 pF, so your existing gate resistor 100 Ohm will give a risetime of Vgs of around 150 ns.
That might be OK, normally 10 to 20 Ohm would give a faster rise time to 18 V or so.

[mbennett555]

David Hess said:

Vgs does not change, however the gate charge required to turn on or off increases by a lot when the Vds changes because of charged pumped through the reverse transfer capacitance.  The amount of charge is so great that at high voltages, the reverse transfer capacitance dominates the input capacitance despite being several times smaller.

That's very interesting.  Based on the scope  waveforms that I posted, I thought that something like that might be going on.

Can you recommend to me a (text)book on solid state electronics that you like?  I gave away the textbook that I had for a course I took at Univ Of Illinois Urbana, in the 1980s.  Although it was from a good publisher, it was thin, and I don't think it was a great book.

Thanks for the info.

[mbennett555]

From the second scope image you've attached, I suppose the 22V rail is derived from de 120V rail that is on the high side of the load. I assume this because that brief 12A spike made the 22V rail tank along with the 120V rail.

The PSU probably isn't able to cope spike - or at least, isn't very happy - with that 12A spike, so C302 and C202 are doing their jobs as decoupling capacitors. If the capacitance of C302 is smaller in comparison with C202 (which is in parallel with VGS and the gate capacitance, which is negligible) and the resistance R102 is small, C302 will be discharged sooner, introducing that glitch you see with the load turned on. That explains why there is no glitch without the load: the PSU voltage doesn't tank and the decoupling capacitors C302 and C202 stay charged.

As I said in my earlier post (about 8 hours ago), I think you brought up an excellent point.

Today:  1) I plugged the power cord for the DC power supply that supplies the 22 VDC bus into a 120 VAC circuit at my house, fed by, I'll call it L1; where L1 has a voltage of 120 V with respect to neutral.  2) I plugged the power cord for the DC power supply that supplies the 120 VDC bus into a different 120 VAC circuit at my house, fed by, I'll call it L2; where L2 has a voltage of 120 V with respect to neutral; and the voltage between L1 and L2 is 240 VAC.  Like most houses in the US, mine has 120/240 VAC service. 

I then set up the circuit so that its load will draw IDS= 3 A, in the steady state condition.  I still see a glitch, when VGS gets to ~3 VDC.  But now, the glitch lasts for only ~300 us (microsecond), shorter than the glitch shown in the screen capture I posted yesterday.

Shown below are 2 screen captures from the scope that I took today.  For each one, as for the earlier screen captures, the channels are:
•   Ch1 (Color= Wht).  IDS.  (The vertical scale is labeled 2.00 V/div, but the true units are 2.00 A/div.)
•   Ch2 (Color= Grn).  VGS.
•   Ch3 (Color= Ylw).  VDS.
•   Ch4 (Color= Blu).  22 VDC bus for VGS.

Screen 1B.  The image below shows the screen capture for the case:  DC Load= 0 A.  We can see:  1) The green waveform, VGS, has no glitch in it.  2) The blue waveform, 22 VDC bus, has a constant value.



Screen 2B.  The image below shows the screen capture for the case:  DC Load= 3 A.  We can see:  1) The green waveform, VGS, has a glitch, because at VGS~ 3 V, the voltage changes so that VGS~ 0 V for about 320 us.  2) Unlike the similar screen capture that I posted yesterday, the blue waveform, 22 VDC bus, has an essentially constant value:  ~22 V (there is a barely-noticeable drop).



Because there is no discernible drop in the 22 VDC bus voltage, I believe that Mr David Hess has the correct explanation.

Thanks to everyone for the replies.

[David Hess]

Vgs does not change, however the gate charge required to turn on or off increases by a lot when the Vds changes because of charged pumped through the reverse transfer capacitance.  The amount of charge is so great that at high voltages, the reverse transfer capacitance dominates the input capacitance despite being several times smaller.

That's very interesting.  Based on the scope  waveforms that I posted, I thought that something like that might be going on.

When driving the gate with a high impedance source, like a series resistor, the gate voltage rises or falls until the drain voltage starts changing, then charge pumped through the gate-to-drain capacitance, aka reverse transfer capacitance or Miller capacitance, stops the gate voltage from changing until the transistor is fully on or off.  That is sometimes called the Miller plateau and it can be used to detect if the transistor is in the process of switching or not.

Can you recommend to me a (text)book on solid state electronics that you like?  I gave away the textbook that I had for a course I took at Univ Of Illinois Urbana, in the 1980s.  Although it was from a good publisher, it was thin, and I don't think it was a great book.

I have a few textbooks but they are all older than 1980, and I wouldn't recommend them anyway.

A lot of practical circuit design can be learned from application notes.  None of my textbooks include analysis of practical circuit building blocks except things like differential pairs and maybe current mirrors.

[HiZ]

When driving the gate with a high impedance source, like a series resistor, the gate voltage rises or falls until the drain voltage starts changing, then charge pumped through the gate-to-drain capacitance, aka reverse transfer capacitance or Miller capacitance, stops the gate voltage from changing until the transistor is fully on or off.  That is sometimes called the Miller plateau and it can be used to detect if the transistor is in the process of switching or not.

That's very interesting. I remember reading something along those lines, but that didn't come to mind when looking at the graphs.

If anyone is interested in a more detailed explanation on how MOSFETs and IGBTs switch, and all the considerations that this process entails, I highly recommend Texas Instrument's Application Reports. The one I'm attaching explains pretty much everything I care about MOSFET switching at the very least on a surface level. It's likely the one that made me ring a bell when reading David Hess' post.

[David Hess]

If anyone is interested in a more detailed explanation on how MOSFETs and IGBTs switch, ...

It is not something unique to MOSFETs and IGBTs; bipolar transistors exhibit the same behavior.  At this level of analysis, they are all voltage to current devices which rely on charge.

There are several ways to handle it; the gate or base (and source or emitter) can be driven from a low impedance source which is easy enough to do, a part can be selected which has lower reverse transfer capacitance, or a two transistor cascode connection, which minimizes the voltage change on the drain or collector, can be used.  With bipolar transistor circuits, sometimes a "speed up capacitor" is selected to add or remove the exact amount of charge and placed in parallel with the base series resistor.  FET circuits may do the same thing to control charge injection from the gate to their other leads.

Some circuits like the Miller integrator, commonly found as the voltage amplification stage in an operational amplifier, take advantage of it for their function.