PAL tv sync signals ?

[old gregg]

hi,

I'm working a composite video signal generator (fancy name for a video synth)

the idea is to input modulated signals into a video encoder (AD725) and output it on the tv through composite procotole.

I need to generate Hsync and Vsync (or simply "composite sync") for the AD725 to function properly.

My idea for the first experiment was to use an LM1881 extracting timing imformation from an old PAL Playstation. However for the final project I'd need to make a stand alone sync generator for obvious reasons.

Considering the high number of tv, I'm pretty sure that some manufacter designed chips for this very task. However, no ideas about references, do you have some ?

Another idea was to use a µC clocked with the same 14.7Mhz crystal (needed for the AD725) and generate all the pulses with I/O pin changes (the AD725 is TTL compatible) But I'm not sure if the atmega could be time precise with all the changes.

The others tricky part : the RGB signals need to be put at 0V when the color burst occurs (in the AD725) for a 2.2µS period. Once again I thought about controlling this with the µC.

Anyway, a dedicated chip for all this could be really nice and save so much time.

do you have any experience with PAL tv protocol ?
Any experience with the AD725 ?
how to generate the sync pulses ?
Any advices , ideas ?

thanks


 

[kolbep]

Raspberrry PI has composite output.
Depending on the project, maybe you could just use a RPI with more software coding, then hardware hacking?

P

[bktemp]

The AD725 needs a 4x fc clock -> 17.734 475 MHz for PAL.
There are many projects on the net generating a b&w video using a small AVR or PIC controller.
It should be easy to just generate the sync signals. For HSYNC you can use the PWM output most controllers have. Just set it to the appropriate timings. If it has multiple outputs use another channel to generate the blanking interval.
If you clock the uC at 16MHz the needed division factor is exactly 1024: 16MHz/1024=15.625kHz.
Since VSYNC is only at 50Hz it can easily done in software by counting the lines during hsync.
Almost all tvs work with this simplified sync signal (HSYNC and VSYNC XORed together).
If you need to generate a true PAL signal with both half frames it is a bit more difficult to generate the serration pulses, but a uC clocked at 16MHz should be fast enough.

[old gregg]

thanks for your answers guys !

I don't want to use a Raspberry pie for this. It's a bit overkill and I'm not that skilled yet to code such thing. Can Raspberry be used with C language  or is it only python ?

The AD725 needs a 4x fc clock -> 17.734 475 MHz for PAL.
There are many projects on the net generating a b&w video using a small AVR or PIC controller.
It should be easy to just generate the sync signals. For HSYNC you can use the PWM output most controllers have. Just set it to the appropriate timings. If it has multiple outputs use another channel to generate the blanking interval.
If you clock the uC at 16MHz the needed division factor is exactly 1024: 16MHz/1024=15.625kHz.
Since VSYNC is only at 50Hz it can easily done in software by counting the lines during hsync.
Almost all tvs work with this simplified sync signal (HSYNC and VSYNC XORed together).

I'm not playing clever at all, I'll use the recommended oscillator type (74CH04 with the proper 17.734 Mhz crystal) needed for the AD725. I'm waiting for the hex inverter.

the thing is, do I need the seration pulses? I read (or think I have) that serration pulses can be removed with non-interlaced signal (which makes sens). Otherwise they could be produce with a PWM.

All the modules that will create and modulate the RGB signals will be analog I only want the µC (or a dedicated chip) to produce the sync signals for the AD725.