Multislope Design

[Rerouter]

Also been looking into DA, and wow are the capacitors cheap, just at the cost of size,

https://au.mouser.com/datasheet/2/440/e_WIMA_FKP_2-1139852.pdf for 26c (Poly propelene),

I suppose at these modulation frequencies Dissipation factor would also come in to play. however both PP and COG seem in the same ballpark, with COG just being more stable vs frequency. with the poly winning by a factor of 20 to 50 on dielectric absorbtion

edit: also find it a little weird that PPS capacitors do not list dielectric absorbtion,

edit2: also found a link to how to design a circuit to compensate out DA, not sure if it would be a benefit though,
https://electronics.stackexchange.com/a/289322

[Kleinstein]

I have not yet implemented reading the exact moment of the comparator switching (using the input capture function). Reading the time is the simple part. The slightly tricky part is than to switch with a fixed delay from that time. I think I got a working code for this, but not yet tested. The idea is to add 2 delay steps of 1 and 2 cycles depending on the last 2 bits of the ICP result.
This improved accuracy for control should allow to get away without the slow slope if the µC runs at a fast clock (e.g. >=12 MHz).

However the timing resolution does not effect the way the result is calculated. For the conversion the relevant time is not the point when the comparator switches, but the time when the output is switched.

The fast part of the run-down only takes some 40 µs, but there is also the slow part, that may take some 10-15 µs as there is quite some overshoot. Than comes some waiting time (e.g. 40 µs) to give the amplifiers and fast part of the DA time to settle. The final required part is some 15 µs for the sampling part of the AVR internal ADC.

For combining the result of the run-up and fast rundown, it helps to keep in mind that the main reference level is the difference from the positive to negative side. So a 20 µs interval from the run-up gives 20 µs worth of the difference. For the rundown the difference in the times for the positive and negative reference active has half the value. E.g. having some 1 µs neg. and 15 µs pos. would be 14 µs difference, that has the same effect as 7 µs of the difference. The sum of the times for the positive and negative active than is part of the slow slope contribution. If no slow slope is used it would be still a correcting parameter if the reference are not exactly opposite.

The charge injection and leakage currents at the switches act as additional input current. So this is just like an offset to the input. So it is not separately measured, but corrected with the OPs offsets etc. by taking the difference to a zero reading.

For the DA there should be no need to do a correction like shown in the link. From the estimates the DA effect should be small enough. If a correction would be done, it would be more by modifying the control during run-up, so that the average integrator output voltage is smaller. The HP34401 does this by adding some negative part of the input signal to the comparator voltage. From my estimates not even this is needed. The DA values of different bands / types vary quite a bit. So it may be easier to get a good cap instead of adding more circuit. With only some 1-3 nF there is plenty of choice. I kind of like NP0 because of the small TC. There is still the option to use a slightly faster modulation.
.
The DA usually is caused by 2 processes: a fast one with a time constant roughly in the 10 µs range. This part is usually material internal reorientation of dipoles. With the extra waiting time this effect should not matter much in my implementation.
 
The second part is very slow with a time constant more in the 10 s range. This is usually assumed to be due to surface charges in the capacitor. This part of the DA may vary between capacitor brands / types, e.g. with different amounts of air or humidity trapped inside. This part is also the relevant part for the ADC. The main effect is to kind of hide some charge proportional to the average integrator output voltage and give it back later. So the important number is more like the DA at 1 second. As a crude estimate the expected DA related error would be in the ball park of DA at 1 second divided by the modulation frequency in Hz, so something like 0.1% / 50000 = 0.02 ppm. Much of this would be a carry over from one conversion to the next, not directly an INL error. A linearity error can happen especially in the center of the range as the average voltage there varies with input.

[Rerouter]

Oh the joys of math, now working through rundown, 45uS is the maximum time required for a fast rundown based on the current parameters, which gets you an uncertainty of 27mV, (comparator could flag in the jump instruction or after the compare state was read)

Slow slope is another 3uS maximum, this gets you to an uncertainty of 1.3mV (2 clock cycles again)

For both of these, you will end up with a fairly fixed offset of 2 clocks, 1 for the response to switch the output, and ~1 for the delay to switch the mux, so that potentiometer for the AVR analog input is most effective when trimmed to a level about 2 clock cycles below the ADC's beginning of range + uncertainty, or about 0.75V

then an ADC conversion to drag those last few bits out. but it seems limited right now, as you said you expected this to reflect 5uV  per LSB, it would be a simple case of altering the gain resistors at U13 to ensure it encompasses say 4 times the slow slope uncertainty, meaning right now it should be possible double its gain and remain in range. e.g. 2.5uV / LSB 

[Kleinstein]

The timing steps are 4 clock cycle. This is the time for the loops checking the comparator. The time it than takes to than actually switch only gives an offset / shift.  Due to the shift and resulting oveshoot the slow rundown takes a bit longer. To reduce this there is the option to add a level shift using resistor between PD5 and PD6. However the extra time may not be that bad, as it's already near the target and thus already helping the amplifier settling. The variable part of the slow slope part can take some 250 ns times the slope ratio, so up to some 5 µs.

The residual voltage levels sound plausible. Resolving the 1.24 mV rest after slow rundown to some 5 µV only needs some 8 bit from the final ADC. So there is quite some headroom, as the ADC has 10 Bits.  The trimmer at the comparator is used to bring the ADC readings in range - so it is relatively easy (not critical, just inside a rather large window) to adjust.
So far the level is quite stable and I see thus little problem with hitting the rails / limits due to drift / aging.

Less asymmetry in the references could be used - the main advantage I see is a higher reference level and less effect of the divider for the shift. The extra resolution is not really needed. If needed less gain at U13 could be used too. For the normal 20 ms conversions the noise limit is at more like 50 µV for the integrator voltage. So a 5 µV resolution is not really needed. It may help for faster conversions ( e.g. 1 ms). Doing a 2nd conversion for the µC internal ADC gives essentially the same reading - so the readout noise is at or below the 5 µV level.

It is more like there is enough room to use more of the µC ADC resolution and than get away without the slow slope, if the timing resolution can be reduced to 1 cycle. So one would gain a 2 bits from better timing, loose some 4.5 Bits from the slow slope and use 1 bit more from the ADC. So some 1.5 bit less of theoretical resolution, but still better than the noise limit.

[Rerouter]

Ok, if that is the case, we can forget the level shift, I like the asymmetric references, so no issue there, was just thinking of twaeking the ratio, but with the new info, it can likely be left as is,

If we tweak the ADC diff amp offset, we can move the comparator into its temperature insensitive range (about 1V), to edge out a little more stability of its switching point,

as for the assembly, it seems it is 3 cycles of uncertainty, should have double checked, RJMP is 2 cycles, and a false SBIS is 1 (assuming the comparitor fired at the exact moment before SBIS would treat it as true)

Code: [Select]

loop:         SBIS    ACSR, ACO ; Skip next instruction if ACO = 1
RJMP    loop         ; Go back to loop
However silly me forgot this is uncertainty in the overshoot, not the timing value, with is 1 clock cycle (using timer capture)
with this, the fast slope is down to 15mV, and the slow slope down to 620uV, if we set up the ADC to measure say a 30mV range, that is a 30uV LSB, so below the noise limit for the current hardware, but just barely.

[iMo]

Fyi - the simulation with KL modulation (3x100k and 560pF, 1us+1us+18us).

[Rerouter]

Apart from the polarity being reversed, looks like my calc is pretty spot on,

If you want to play, have fun https://docs.google.com/spreadsheets/d/124oaWnT20oyATqJzljLi7ERs9dDA7BqPNQoNRmwFV4k/edit?usp=sharing

[iMo]

CountN and CountP within a 20ms measurement:
Imagine we've got 1+1+18us=20us "phase", 1000 phases in 1measurement (1PLC).
With 0V input you have to count CountN=500 and CountP=500.
With 10V input you have to count, for example, CountN=100 and CountP=900.
With -10V input you have to count, for example, CountN=900 and CountP=100.
With 11V input you have to count, for example, CountN=60 and CountP=940.
With -11V input you have to count, for example, CountN=940 and CountP=60.
Or something like that..

[Kleinstein]

...
as for the assembly, it seems it is 3 cycles of uncertainty, should have double checked, RJMP is 2 cycles, and a false SBIS is 1 (assuming the comparitor fired at the exact moment before SBIS would treat it as true)

Code: [Select]

loop:         SBIS    ACSR, ACO ; Skip next instruction if ACO = 1
RJMP    loop         ; Go back to loop

With some µCs this could in deed be a 3 cycle loop. However the Mega48 and most newer AVRs can not use SBIS with the internal comparator as the ACSR register is out of range. So it needs an extra  IN R...,ACSR  instruction.

For the fine delays from the ICP value a 4 cycle loop is also easier. With added delay one could get single cycle resolution - so more like 8 mV at the integrator. So the ADC could cover something like a 15 mV range. So the resolution would just enough to keep quantization noise low. However there would be little reserve for faster conversions. So while is helps to get an even faster rundown, it also limits the resolution for fast conversions.  I would still keep the option for the asymmetric references - one can still populate just 1 resistor to get a nominally symmetric reference.

I think the temperature sensitivity of the comparator curve is more like a typical curve, not one to take to accurate. The comparator is only acting after the slope amplifier, so that the comparator drift is not that critical. The ADC covers some 200 -500 mV of the slope amplifiers output. So the comparator drift has to be compared to this number. So even 10 mV of drift of the comparator would be only some 2-5% of the ADC range.

[iMo]

The measurement of that voltage at the slope's amplifier could be a challenge, imho.
See below ADC input vs slope's amplifier output.

[Rerouter]

I was more suggesting the comparator change, as its a free modification, change R34 to 56K and AIN1's pot to ~1V, and the ADC diff amp resistors accordingly, and you move it into that range, with no layout changes, for now I'll leave it as a schematic note, was just to remove uncertainty if weirder modulation schemes where used

And the assembler timing is actually non critical, as the timer capture is 1 cycle at most, the assembler delay is variable by up to the entire register checking loop, and this will appear as an offset, however you can use the timer capture to bring this uncertainty down to 1 cycle, (you still do not know exactly when in the cycle it tripper the comparator), so lets say if you used a correction pulse of that length, luckily these uncertainties are not independant, so you end up with a fairly fixed uncertainty of just +-0.5 cycles for the measurement with those correction pulses.

Per clock cycle the fast slope adds up to 15.2mV, so the ADC range would be still have to be at least double this to ensure it never leaves this boundary, the less variability there is on the comparator switch point, the tighter we can keep the ADC range without having to worry

All this math is still based on 25K ohm input resistors and 2.2nF integration cap, these slopes can be changed a little if you wish, I have updated that google sheet so you can offset the comparator transition point,

As to IMO, those 1000 high / low descisions are not the only information you have on hand, you also have the timer capture hardware, so you know exactly what clock edge it transitioned on, so instead of 1/1000, it is 1/320000 ok, so 18.25 bits there,

[Kleinstein]

With the fine corrections from the ICP register, one should not need extra pulses - it is just delaying the time when to switch of. Bit 0 would cause an extra

[iMo]

As to IMO, those 1000 high / low descisions are not the only information you have on hand, you also have the timer capture hardware, so you know exactly what clock edge it transitioned on, so instead of 1/1000, it is 1/320000 ok, so 18.25 bits there,

Afaik the 20us phases are fixed length, where that 320x comes from?
20us/62.5ns=320?
1000x(+/-0..62.5ns)=+/-0..62.5us
Is your resolution 20ms+/-0..62.5us then?

[Rerouter]

20uS is the pattern length,but the timer is running on 16MHz, so 1us = 16 timer counts, The hardware comparator and timer capature will fire when it crosses its switching point, capturing the time it changed at, giving you resolution based on that 16MHz clock, not just the pattern cycles.

To my understanding the pattern is mainly to ensure both references get used a similar number of times every conversion, however this seems fairly variable to me. and there is no real solution around it,

on my sheet you can see how Count+ and Count- are not always a count of 16, these are the 0 crossing moments, this is because the capture function on the timer would have triggered, and that is the captured time for that 1us step of the pattern.

[iMo]

  That has to be understood well, I have not dug into the assembler, but I tried to capture the algo in one post in KL's thread, it seems to me now the algo is different then..

[Rerouter]

Its more me doing my best to interprit it, He is using and reading from the capture register, and it comes inline with his ~18 bit contribution from the modulation phase.

also found the 1st magic value where this method can go badly, -0.6V on the current reference levels is perfectly inline with the reference contributions, so the modulation pattern is just +-+-+-+-+-+-, but the duty cycle of the timer pulses is 94.4%, and implies it would be there for a few other values where this can hurt things. up side is keeping track of the pattern switches, can be used to correct these magic values as they appear.

edit: may only be the 1 gap, as with symmetrical references, this would be the 0 point, or the average of the 2 reference voltages, so it makes sense that only at this sliver of the range it would not be able to resolve using the normal method, instead it would be inverted in a sense, but you could still resolve it, seems to be about -0.76 to -0.46V

[Kleinstein]

The main purpose of the patterns in the run-up is to make sure that the number and type of switchings of the 4053 are the same independent of the input voltage. This ensures that charge injection only gives an offset.
There are other options to implement this part. The 3 step pattern type are just the simplest solution. Other systems like a more continuous PWM system could be used too, but are more difficult to control.

Currently I am not yet using the ICP function. So the timing resolution is currently "only" 4 cycles = 250 ns. Here I just use the timer register to get the current time as the program runs.
The initial part comes from the run-up. Some 850 patterns of some 20 µs each.
The next part is the fast rundown that gives some 20+ µs with 250 ns resolution. Here only 1 reference is active and thus the effective time resolution compared to the positive or negative double.
Together with the run-up this gives some 0.9 * 20 ms/250ns *2 = 144000 counts of resolution as the first contribution.

The next part is than the slow slope part, with a slow slope of about 1/20 and the same timing resolution. This second contribution gives another factor of about 20 to the resolution. So together this more classical multi-slope part, using the comparator gives a resolution of some 2.8 million counts, so about +- 6.5 digits.

The final part is than the µC internal ADC: this gives some 8 bits of nominal resolution. However noise limits the effective resolution to only some 3-4 bits from the µC internal ADC.

The -0.6 V range is indeed one of the more critical ranges. Much of the early test where about this slightly difficult range. There is nothing principle bad (like miscounting the coarse part) happening. The center point was a problem (INL errors in the 1-10 ppm range) with the slightly more complicated 4 step method initially used. The 3 step pattern made things much (more than a factor of 10) better. There is still a little of INL error of the same kind visible in my test, but at a rather low level (e.g. < 0.1 ppm).

[Rerouter]

Well I can at least say what I feel is the common tell tale, if there is never 2 of the same pattern in a row, it is in this middle area, if there is only 1 polarity of the pattern used, it is out of range, trying to make nicer the math to cope with this middle area. technically all the info to resolve it is there, just it currently has to be treated differently.

The basis of the math looks to revolve around if the first pattern was positive or negative, then using the dutycycle to tell where it was in that range, but the positive and negative responses need to be handled differently, as slightly less than -0.6V gives a duty cycle of almost 0, and a value slightly more than -0.6 gives a duty cycle of almost 100%, moving towards 50% the closer they get to the end of this magic range. (offset of 2 patterns over 20ms)

Edit: the exact center point of all this fun is ((refp +refn) / 2) + integrator offset voltage

[Rerouter]

Hmm, I can see why for the modulation it would be difficult to fit in, due to being 16 bit variables and all, technically it would be 8 - 8 then saved to a 24 bit number, and the real pain is that there can be up to 3 crossings in the same pattern, so however it was handled would need to happen in each pattern step, of which I'm unclear how many free instructions are left, and how far the modulation can be taken without effecting other things if the step size was increased.

[iMo]

In January we were discussing the schemes and I was suggesting here in the post to gate a fast clock simply by the P and N phases into two counters. Thus a combination of the KL or Jaromir's patterns and counting the charge balance with a high precision may work best for the runup.

PS: the "PWM" in my post in the link is perhaps misleading, it is more-less a standard modulation.

[iMo]

@Rerouter: your Excel sheet - you are splitting P and N counts based on the signal slope at the transition moment (crossing the zero). But I see there you are counting Count- even the switch is Positive, and vice versa.. Why? I think when the ref is P you have to count 16 for the Count+ always, and if the ref is N you have to count 16 for the Count- always (except they are split).

[Kleinstein]

Hmm, I can see why for the modulation it would be difficult to fit in, due to being 16 bit variables and all, technically it would be 8 - 8 then saved to a 24 bit number, and the real pain is that there can be up to 3 crossings in the same pattern, so however it was handled would need to happen in each pattern step, of which I'm unclear how many free instructions are left, and how far the modulation can be taken without effecting other things if the step size was increased.

With the 2 fixed phases in between, the center of the range is not that special. It is going between positive and negative and back, just the time moves around a little. So in the run-up it is just counting the positive 20 µs chunks and the middle is not special in this case. The integrator should be fast enough that the short pulses with 1 µs should not be any special. So no need to extra count those extra for possible corrections for possible settling effects.

Like IMO wrote, this is just the normal modulation - it looks like the HP34401 and 3458 use a similar mode, just with a higher frequency.  The frequency is still a parameter that could be changed - there should be room to reduce the 1 µs fixed parts, if the integrator is well tuned.
One could directly add the times during run-up (e.g. add some 20 µs = 320 clock cylces on each comparator dependent phase). It the times are all the same, it is enough to just count one case (e.g. positive) and than at the end multiply by 320 (or what ever is the length). I just send the raw number and let the PC do the math. This helps a little with debugging.

[iMo]

 

@Kleinstein: Now, let me doublecheck following re the scheme of the pattern (as has been discussed in your thread) with two subsequent patterns:

Code: [Select]

PatternN1   1. you set refN for 1us
            2. based on the comparator's output you set refP or RefN
            3. you wait 18us
            4. you set refP for 1us
PatternN2   5. you set refN for 1us
            6. based on the comparator's output you set refP or RefN
            7. you wait 18us
            8. you set refP for 1us
PatternN3   9. you set refN for 1us
...Is this correct?
Am I missing something?
Is the comparator read only once in each pattern as described above?
What is the "variphase" in your asm?
At which points above you start and finish with the capturing the "phase duration"?

[orin]

The DA usually is caused by 2 processes: a fast one with a time constant roughly in the 10 µs range. This part is usually material internal reorientation of dipoles. With the extra waiting time this effect should not matter much in my implementation.
 
The second part is very slow with a time constant more in the 10 s range. This is usually assumed to be due to surface charges in the capacitor. This part of the DA may vary between capacitor brands / types, e.g. with different amounts of air or humidity trapped inside. This part is also the relevant part for the ADC. The main effect is to kind of hide some charge proportional to the average integrator output voltage and give it back later. So the important number is more like the DA at 1 second. As a crude estimate the expected DA related error would be in the ball park of DA at 1 second divided by the modulation frequency in Hz, so something like 0.1% / 50000 = 0.02 ppm. Much of this would be a carry over from one conversion to the next, not directly an INL error. A linearity error can happen especially in the center of the range as the average voltage there varies with input.

Don't be surprised if you find a time constant of some 25 ms too.  That's what I found for the integration capacitor in my 3455A.  Picture here:

https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855

New WIMA MKP 4 were no better, nor was an NP0 that I tried.  Only an absolutely huge Russian teflon capacitor was significantly better (see traces in the above post).

[David Hess]

Last time I checked this, I found considerable variation between brands of capacitor with the same dielectric and sometimes between lots from the same manufacturer.  High voltage safety capacitors tended to be worse.

So I suggest testing polypropylene parts from several different manufacturers.  It is too bad Teflon parts lack good availability.