I was more suggesting the comparator change, as its a free modification, change R34 to 56K and AIN1's pot to ~1V, and the ADC diff amp resistors accordingly, and you move it into that range, with no layout changes, for now I'll leave it as a schematic note, was just to remove uncertainty if weirder modulation schemes where used
And the assembler timing is actually non critical, as the timer capture is 1 cycle at most, the assembler delay is variable by up to the entire register checking loop, and this will appear as an offset, however you can use the timer capture to bring this uncertainty down to 1 cycle, (you still do not know exactly when in the cycle it tripper the comparator), so lets say if you used a correction pulse of that length, luckily these uncertainties are not independant, so you end up with a fairly fixed uncertainty of just +-0.5 cycles for the measurement with those correction pulses.
Per clock cycle the fast slope adds up to 15.2mV, so the ADC range would be still have to be at least double this to ensure it never leaves this boundary, the less variability there is on the comparator switch point, the tighter we can keep the ADC range without having to worry
All this math is still based on 25K ohm input resistors and 2.2nF integration cap, these slopes can be changed a little if you wish, I have updated that google sheet so you can offset the comparator transition point,
As to IMO, those 1000 high / low descisions are not the only information you have on hand, you also have the timer capture hardware, so you know exactly what clock edge it transitioned on, so instead of 1/1000, it is 1/320000 ok, so 18.25 bits there,