Multislope Design

[Kleinstein]

@Kleinstein: Now, let me doublecheck following re the scheme of the pattern (as has been discussed in your thread) with two subsequent patterns:

Code: [Select]

PatternN1   1. you set refN for 1us
            2. based on the comparator's output you set refP or RefN
            3. you wait 18us
            4. you set refP for 1us
PatternN2   5. you set refN for 1us
            6. based on the comparator's output you set refP or RefN
            7. you wait 18us
            8. you set refP for 1us
PatternN3   9. you set refN for 1us
...Is this correct?
Am I missing something?
Is the comparator read only once in each pattern as described above?
What is the "variphase" in your asm?
At which points above you start and finish with the capturing the "phase duration"?

The shown program is about how I use it. The comparator is only reed once for each "20 µs" phase, even a little before the constant phase.
The "variphase" part in the ASM code is the core part of the comparator dependent part, especially counting the number of positive cases. The code may be a little confusing because the actual comparator test is split in 2 parts: first read the comparator to a CPU register (t3) and only later test the register in a makro ( #define skipCompPos  SBRS t3,ACO   ). The macros are used to allow changing the hardware to negative reference more powerful than the positive without doing to many changes in the code. My HW on the breadboard initially was this way around.


For the integration capacitor, I have tested a few so far: 3 different, old PS type caps and 2/3 x 1nF NP0 (THT version) caps in parallel. They work reasonably good with very little visible DA effect. I also tried some low quality caps (MKC, MKS) and these show quite some DA effect - so much to even tend to leave the range of the µC internal ADC. So it kind of worked for a small range. For the PP caps I expect some possible difference between units, as the critical part is the slow DA. AFAIK this is the DA due to the surface effects and thus production dependent.  Finding good caps may still need some trying.
Compared to classical dual slope ADCs, I don't care about the very fast part - though this should mainly be a dielectric property, and thus the easy part.

 

 

[Rerouter]

If you have already broken out the flag to a register. You could likely make it PWM without much change.  To lock the number of switch cycles to always be the same
Positive pattern: 1uS positive fixed. 18uS positive variable. 1uS negative variable
Negative pattern: 1uS positive fixed. 19uS negative variable.

[iMo]

Thanks. I've been asking on the exact run-up patterns scheme because you often use wordings with "..variable.." (ie. see the above post).

There is not "a variable phase" in the run-up patterns today (based on the above confirmation in the post #400), all events related to the switching of the Positive or Negative reference voltages within a pattern happen exactly at fixed specific times and are of fixed exact duration.

The P and N ref_voltages run-up switching timing is therefore not based on the "zero crossing" information.

One may wonder where the 18.5bit run-up resolution comes from when all the events in the pattern happen at exact fixed times and are of fixed duration (and therefore the charge balance is given by the number of active Ps and Ns within say 20ms frame).. 

How the additional run-up measurement of the "exact" time between the two "zero crossings" improves (xxx times) the balance calculation?

Could you elaborate on the exact principle/formula, plz?

[Kleinstein]

The variable part part is kind of either positive or negative. So the name may be confusing.

The resolution from the run-up part is limited. I get something like 1000 counts, so about 10 Bits. Even with more intermediate steps the resolution would not be that much higher, as there is the residual charge at the end of run-up as a limiting factor.
The 18.5 Bit resolution level is reached after the fast part of the rundown: this brings down the step size from some 20 µs to some 250 ns with half the reference weight. This gives a little more than 8 Bits. To the resolution. A faster modulation during run-up could give a little more resolution there but reduce the part from the run-down. It would not change much of the combined resolution that is given by integration time (e.g. 20 ms) divides by time resolution (e.g. 250 ns) times 2. The extra factor 2 comes from having either a positive or negative reference. Some of the integration time is effectively lost to the fixed phases - so some 10% of the resolution is lost.

The timing of the zero crossings could (with sufficient processing power) be used to get finer feedback during run-up. This gives more resolution from the run-up part, but it reduces the part from the rundown. It may still be helpful, but not for more resolution. A more accurate feedback reduces the average voltage and this way get less of the slow DA effect.  The Solartron DMM kind of uses the exact timing of the zero crossings and a continuous integration with no rundown - however this is a different type of ADC.

[iMo]

Ok, so my example above with 1000 P+N counting is still valid for your run-up (we still discussing the run-up only) and it is basically what you get today in the run-up. The additional information for improving the resolution comes from the rundown and from the info on the residual at the beginning (and the end) of a measurement (the measurement = 1PLC = 20ms).

[Rerouter]

my rambling are not kleins', I'm just trying to infer each part of how these work,

My understanding of it is, lets say you feed in 7V, by feeding it though a fixed resistor we get a current or coulombs per second, in this case 70uA for 20ms, so removing the time component is 1.4 micro-coulomb,

You need to cancel out that amount of charge to get the integrator back to the switching point of the comparator, of which you have 2 other voltages you can feed through a resistor to cancel that charge,

In our current case that is 13.4V (2.68 micro coulomb), and -12.2V (-2.44 micro coulomb), it may be easier to think of these as 2 lines of a fixed slope,

Your trying to measure as best you can the ratio of these 2 that cancel out the charge, while still adding up to 100%, e.g. 40% negative and 60% positive. of which there is only 1 point it can happen, you can see this in the modulation pattern if you imagine first using all the positive bits, then using all the negative bits,

The pattern is mainly there to ensure at least 1 step of the opposite reference every now and then, for charge injection reasons, (or so I assume) but could also be to deliberately make the integrator go a bit further from 0,

so lets say you only counted the modulation patterns, a total of 1000 for a 20 step pattern, you can think of it like a triangle with a hypotenuse of 1000, with the +Count and -Count representing the contribution of reference, now that duty cycle is a fixed number after your conversion, but as its rare it will perfectly cancel with only those 1000 pattern steps, you are left with some residue, in the example image, you would use this to extract extra information, and move the true duty cycle amount to correct out that residue,

I was trying to determine this point by using the zero crossings to sum up the ratio of time above 0 (an excess of charge has been removed), and below 0 (there is still charge to be removed) to extract more information out of the pattern, on top of the residue, in a sense trying to make it behave like a much faster modulation frequency, but was still unwrapping the math on it, as its not as clear to imagine as the residue example. best example would be capturing lots of smaller triangles, and using them to reduce the uncertainty of the total count / residue

The PWM approach I was describing above could be used as a true PWM, by changing the ratio of positive and negative. per pattern, but in reality, the steeper the slopes those references contribute, the more information that can be extracted by the residue, as if you imagine it, if this triangle was a lot taller, moving that duty cycle to the left to remove the residue moves the duty cycle point less, with the most usable information extracted when that residue contributes only about 1-2 counts,

[iMo]

@Rerouter: Sure, the "PWM" like pattern was the thing we discussed a while back, and it is still a pretty sexy solution for how to improve the run-up resolution, imho. I even tried with simulation but had problems with keeping the integrator in the range (my naive approach perhaps).

I was thinking you really do some improvements of the run-up resolution in the current fw (with the additional zero-crossing timing information) therefore I asked.

I can imagine myself to use an FPGA, do the "fixed time pattern schema" as it is today, and, to timestamp the zero-crossings with 1 clock resolution (say 10ns), to save all the timestamps into the FPGA's memory, and (after the run-down) to provide the final calculation with the set of timestamps saved.

The question is how to incorporate the zero-crossing (run-up) information into the final calculation.

[Rerouter]

The zero crossing information would be used to reduce the uncertainty of that final count value to a fraction of a count, e.g. using an example of 7V, (I am fixing up my calculation to reflect this)

etc...

the first triangle is 16 Count+ | 62 Count-, 20.5%
the next triangle is 65 Count+ | 258 Count-, 20.12%
Third                     303 Count+ | 1197 Count-, 20.20%

you can also use the sums of each triangle, e.g total for those 3 would give, 20.199%
after you have all of these, you get the deviation, weigh them by there uncertainty, and can use that to shift the final count a little before the residue is applied.

[iMo]

@Kleinstein: do you switch the ADC's input off during the short 1us_P+1us_N phases within the pattern (run-up)?

@Rerouter: isn't it such that all that zero-crossing uncertainties within 1000 patterns transform themselves into the final run-up residual as an offset?

[Rerouter]

I'm trying to work that out, the math is a pain for someone who never took calculus, and it may end up being a below the noise contribution,

Edit: the residue is due to discrete correction steps in the form of the entire pattern, but it may end up being about the same

[Kleinstein]

For the current multi-slope ADC with rundown phase, the exact timing of the zero crossings does not give extra information on the DC voltage. The only part of the run-up that counts is the charge added from the references.

The position of the zero crossings in theory has some information about higher frequencies present, but his would be a mess to extract and we a usually not interested in those higher frequency part.

In theory the timing could be used in a different type of ADC, using only the run-up and the exact timing. This is about how the solartron DMMs work. However this is a different kind of ADC with limited resolution (or very slow).

The timing could be used to a more accurate feedback during run-up. However this is not easy and it would not help with overall resolution. It could help with keeping the average integrator output voltage more constant and this way reduce the DA effect.
I have a crude idea for a more PWM like feddback - however it is too slow for the AVR - more like something for an ARM or FPGA. Still I doubt it is worth the effort for maybe a fat 2 smaller cap and a reduced DA effect that should be quite small already.

[Kleinstein]

@Kleinstein: do you switch the ADC's input off during the short 1us_P+1us_N phases within the pattern (run-up)?

@Rerouter: isn't it such that all that zero-crossing uncertainties within 1000 patterns transform themselves into the final run-up residual as an offset?

I only use the µC internal ADC in the run-down phase and with the integrator in hold mode when sampling.

[Rerouter]

well at least for the AVR limitations, you may be able to extract some more info by doing a modulated slow rundown to reduce the average slope,

edit:it would still leave us at pretty much the noise limits you have given... Now I suppose to figure out how to actually sum that up from what we currently have to cross check it. see if we have nay room for improvement, and to work out how much PSRR will hurt it.

edit2: this leaves open the question of what bandwidth range we need to calculate the noise across. for the reference that is pretty easy as that is heavily bandwidth limited, but the ADC is less clear,

[iMo]

@Kleinstein: do you switch the ADC's input off during the short 1us_P+1us_N phases within the pattern (run-up)?

@Rerouter: isn't it such that all that zero-crossing uncertainties within 1000 patterns transform themselves into the final run-up residual as an offset?

I only use the µC internal ADC in the run-down phase and with the integrator in hold mode when sampling.

I mean - do you switch off the input of the MS ADC - the "input of the integrator" during the 1us+1us run-up phases?..

[Rerouter]

Everything points to it having the input always on for the entire 20ms period, then off for the run down, the references having a ferrite bead I take as a hint,

Now for the noise calcs, will involve working out the bandwidths of interest for the various ADC parts,

reference noise is mostly done, with the LM399 being the dominant noise source, by about a factor of 10,

[Kleinstein]

@Kleinstein: do you switch the ADC's input off during the short 1us_P+1us_N phases within the pattern (run-up)?
I mean - do you switch off the input of the MS ADC - the "input of the integrator" during the 1us+1us run-up phases?..

Of cause the signal input is not switched off during the 1 µs fixed phases.

A possible target for an improved run-up phase would be to get less average integrator voltage to reduce DA. There may be a few options for this, but one has to be careful not to cause other errors - the 4 step version I initially used was such a "solution" that was a little better with DA, but caused other INL errors.
However I would call this more like a later software option to play with, in case DA turns out to be a serious problem.

The question on which bandwidth to calculate the noise for is a good one. Here it is not only the bandwidth, but also the frequencies of interest as some noise sources are frequency dependent. Even the reference part only gets easy with the extra filter at the input.
The BW and frequency range is different for different noise sources. Also the way of using the ADC makes a difference. The main case of interest would be a simple 20ms signal - 20 ms zero cycle. So the lower frequency limit should be at some 25 Hz. A different (longer) sequence could include lower frequency noise.

One difficulty is going from noise densities for the parts to RMS noise for a conversion or better the difference of 2 conversions in a row.

[Rerouter]

I suspect that may be what C37 and C17 are for, to set the low pass bandwidth of the input, to reduce the maximum frequency range,

as a minimum, our input slew rates give us the bandwidth required to represent that slew rate, with 25K input resistors that would be about 18KHz needed for the op amp to represent it, we can also use pin capacitances to start reducing the maximum bandwidth of each part to get sensible numbers, also working out, but I suspect the modulation actually lets us discard most of the lower frequency noise,

[Kleinstein]

C17 and if used C37 are used for adjusting the settling of the integrator input. So more a question of loop compensation.
C37 may also keep away the very high frequencies (e.g. > 20 MHz) away from the integrator. Both caps sit at a virtual ground point - so they don't act as a low pass with R1,R2,R3.  The effective resistance they see is more the input impedance of the integrator of some 10-100 Ohms.

For the input noise the upper limit is set from the integrating action. The integrator gives an 1/f factor - so higher frequencies get increasingly less important. This reflects the input aperture integrating over some 20 ms and thus the sin(x)/x  response typical for integrating ADCs. This frequency dependency applies to to the input buffer, but also the resistors and the integrator.

The lower frequency limit is set by the AZ cycle, so normally doing a 20 ms conversion of the input and 20 ms of zero reading. 

[Rerouter]

IMO, as you have this modeled, any chance you can run an AC sweep to work out what frequencies we do not have to care about,

The NE5534 thanks to its small signal gain only has a bandwidth of 500KHz, this is what the comparator sees, and the ADC only has a 45KHz bandwidth,

If we assume just this part, then the NE5534 may be up to ~2500 nV of noise, and the ADC amplifier about 6000 nV of noise, just from the devices alone, and seem to get really swamped to crap by the resistors when the BW is still so wide,

My assumption on the actual frequencies would be, that anything below 1/8th a frequency of interest would at most be able to only add half of its amplitude, so a high pass 3db point If I'm not confusing myself, so taking this forward for the integrator, it is based on slopes, the bandwidth required to represent the possible range of slopes is 5KHz to 8.2KHz, so on the low end, we can probably discard noise sources under 625Hz when it comes to op amps and resistors, (PSRR and external noise still count here.)

As for any kind of low pass effect on the high end, I'm wondering exactly where we can draw that line, as if the 1/8th thing holds, it allows us to significantly cut out the low frequency components of the NE5534 (105KHz high pass) but the further this can be reduced the better, (The MCP6002 would not get this as you measure with no effective slope)

[iMo]

IMO, as you have this modeled, any chance you can run an AC sweep to work out what frequencies we do not have to care about,

Below the AC sweep of the integrator and slope ampl. I do not have a working NE5534 handy. Also the integration ampls are the universal models with important params close to the original ones.
EDIT: two versions: 25k + 2n2 and 100k + 560pF

REMOVED - wrong DC offset.

[Kleinstein]

I don't have a good computer controlled frequency generator. So taking AC sweeps from the input would be difficult for me. Anyway the simple integration over a defined window (e.g. 20 ms) is well handled from the theory side.

The noise of the comparator is not critical. Any error the comparator may make can later be compensated by the µC internal ADC. The comparator is only used for a kind of 1st approximation so the range covered by the ADC gets smaller. Noise of the comparator would only enlarge the range to be covered by the ADC. Currently it looks the extra width due to noise is very small, maybe only some 2-5 LSB or so.

The relevant BW for the NE5534 noise is the one from the ADC. The noise from the MCP6002 is relative to the slope amplifiers output, so something like a factor of 20 less critical than noise of the NE5534. The MCP6002 is not low noise, but still not 20 times worse than the NE5534. The relevant frequency band is from some 25 Hz to around 50 kHz. One can experimentally see this group of noise sources, that set the error in measuring the integrator charge. Repeated readings of the µC internal ADC at the end give rather repeatable numbers. This noise is not much higher than the quantization noise of the 10 Bit ADC. So these noise sources would only be a problem with more gain before the ADC (or a lower reference voltage).

The other group of noise sources are those that set the charge actually going in and out from the integrator. Due to the integrator action this noise type gives more weight to low frequencies. The main relevant frequency range is from some 25 Hz to some 100 Hz or so. The main noise sources here are the resistors R1-R3, the integrator (U11), the reference with amplification, variations in charge injection, jitter of the controls to the 4053. A special case here is reference and amplifiers noise in the 50 KHz band, that gets mixed back to low frequency with the modulation. The noise from U11 is amplified by about a factor of 2.

[Rerouter]

It was more to figure out if my theory had ground, however it would appear that it does not, or at least not to the same level I was hoping for, we have a low pass filter on the input to the integrator of about 1KHz, which is nice, as that reduced the noise bandwidth we have to calculate for the buffer amp and similar to practically nothing compared to the rest of the system,

the integrator output has a high pass of about 330Hz, which shaves something off, but not as much as I was hoping to see,

Most of this is me working out how this is calculated without having to lean on spice too hard, and then how to figure out the specific contributions of each tradeoff, you quoted a noise figure, but I do not yet know how to calculate that number for a system like this, so I'm hoping to learn it.

IMO, does anything change if your voltage source is 0V DC with your AC signal?

[iMo]

With 0V DC..

[Kleinstein]

I think the simulations still have some type of flaw, like having the integrator output going to saturation. For the simulation it may help to add a large resistor in parallel to the integrator cap.


@REROUTER: the integrator has the normal 1/f transfer function. The lower frequency limit is set by the integration time.

Calculating the noise is indeed not easy. Part of the problem is that some aspects are better described in the time domain, while other parts are better handled in the frequency domain. When analyzing the system in detail in the frequency domain one likely has to include the input mux and the kind of chopping action done with it.

I have not done a detailed analysis, but only an approximate one.
The main idea also valid for a more detailed analysis is the separation into noise for charge actually going to the integrator and the final measurement of the residual charge. Using the result upfront, the important part is the actual current going in. The residual charge measurement noise is at least for an integration time of 20 ms not relevant. The final charge measurement is also the easier part: in short it is some 25 Hz - 40 kHz frequency range, and noise mainly from U11 (with a gain of 2), the NE5534 and R12. This is some 15 nV/Sqrt(Hz) * 200 Sqrt(Hz) = 3 µV. This noise comes in twice at the start and end of the conversion. The noise is relative to the integrator output and would thus see the integrator gain ( = 20 ms / R3 *C11  ~ 200) for the signal. So for the input this would look like some 2*3 µV/200  = 30 nV.  A faster integrator / modulation could reduce the effect. A much larger integrator cap could increase this noise.

For the current going in, the difficulty is especially the frequency range. This is not just a single range, but a combination of ranges due to the mixing action. The simple approximation is a bandwidth of some 50 Hz (= 1/ 20 ms) and assuming an effective frequency of some 25-50 Hz.

[iMo]

Here is the source, you may play with it.. Added 10Meg in parallel to the integration capacitor.
@Kleinstein: you may suggest the right value for it, plz..