Multislope Design

[jaromir]

Taking measurements of integrator output "on the fly" is possible, and as far I understand, it's done by 80C196 processor. It's got 10-bit ADC and integrator output is routed to one of ADC inputs, confirming this idea. This allows to omit zero comparator and slope amplifier, both being critical components to integrating ADCs. So far so good.
On the other hand, the internal ADC isn't particularly stellar and I can see some compromises being made here:
- S&H sample time is 1,33us (8 states per 167us as it runs at 12MHz) in fast mode, compared to tens us period of modulation frequency.
- ADC has resolution of 1024 levels, but minimal 256 levels - minimum 8 bits, maximum 10 bits of resolution.
- ADC has INL of +-4 LSB
- ADC has DNL of +-2 LSB
- DS requires maximum input impedance 1,2kOhm maximal, but R405 and R407 are 4,16kOhm total. I guess violating this parameter is somehow worsening the internal ADC parameters even more.
I wonder how many bits (or digits of result) are they getting from rundown phase.

The Solartron DMMs has different ADC principle; mark-space type, as described in patent US3942172. I'd say it sits somehow closer to sigma-delta ADCs than to integrating ADCs.

[Rerouter]

Kleinstein what would you have used (or like to have used) for C13?

Never laid out a reference before, But think its coming up quite nicely, still any input would be appreciated,

main goal is just to improve on the layout without increasing the BOM to the level of the LTZ1000 madness.

Only connection left here is to escape the zener voltage to the input MUX, but that is what the third thermal leg is intended for.

[Kleinstein]

For the proposed layout, it would be a good idea to have R4-R7 well matched. These resistors effect the ADC gain and thus the scale factor. So I would at least try to keep them together, or even better use a resistor array  (e.g. AORN, NOMCA, MORN or LT5400-10K). 10 K resistors should also be Ok.

Especially with a resistor array one could consider a slight change: create the asymmetry / slow slope not with R8 parallel to R7, but an extra divider at the + input of U8. Though not that critical, TC matching would matter inside the extra divider and not from R8 to R4-7.

With not so good resistors I currently do a gain measurement for every reading (just like old Keithley 19x DMMs) - this slows down the measurement and adds some noise. It could be still attractive for a low cost version.

For the filter cap C13 a relatively large values is beneficial. I currently have 4.7 µF and R22 now at 5 K. A slightly larger cap (e.g. 10 µF could be used, but they tend to become physical large. As the reference is usually a constant voltage and some warmup is needed anyway polyester cap (e.g. MKS) should be good enough. I would be a little suspicious about MLCC there. To a lesser degree this also applies to C26, C28 but the 100 nF MLCCs may be OK.  As an additional modification the lower side of C13 is now connected to the -13.x V output. This essentially works as a x3 capacitance multiplier. So now I have 3 x 4.7 µF x 5 K  or just short of 75 ms.

The main idea is to have the capacitor to average / filter the reference over the time of a whole measurement cycle (either signal and zero or signal, zero and 7 V). This should help ta avoid some avoidable noise of the reference without too much effort.
As the reference value is not really used in the zero reading this would make it somewhat sensitive to reference noise at around 16 / 25 Hz. This unwanted part is relatively easy to filter out - there is not much to be done about low frequency noise (e.g. < 1 Hz). The main purpose is to get rid of that extra relatively high frequency band that is avoidable. So the target filter time constant should be larger than some 50-100 ms. The minimum requirement for the filter is to keep out the >20 KHz noise, which is easy.

If the MUX in front of the ADC causes significant charge pulses on switching, one could consider an extra buffer for the 7 V to the MUX, especially if the fast gain adjust mode is used.

For the 34401 ADC, I also have some problems to see how they get there resolution for short conversions. The limited resolution of the µC internal ADC may explain that they still use 10 PLC despite of quite some 1/f noise from the OP27.  One method they may use could be reading the auxiliary ADC multiple times and average. This would correspond to a kind of soft ends of the integration time. However this would come at the disadvantage of more time lost in AZ switching. Much of the multislope II ADC is described in US patent 5117227  - though I still kind of miss those details.

[Rerouter]

Any objection to using COG dielectric for the 100nF capacitors in this part of the circuit. Those polyester are big, Can certainly do for C13 as Its value rules out COG but for all other specs seems like its just as suitable

I can lay out for a resistor array, I suppose the question is how much do they cost and please give an exact model and I'll lay it out. (Should it not be a 5K array?)
e.g. I see this and would think its suitable, but you may feel differently, (Try and pick something that is normally stocked)
https://au.mouser.com/ProductDetail/Vishay-Beyschlag/ACASA5001U5001P1AT?qs=sGAEpiMZZMvrmc6UYKmaNaT%2FGf4mI0tTOw5gJ49cnpM%3D

If we need a better ADC for the residue, that is not a problem, Make use of the adjustable ADC Vref in the arduino to get the resolution where you need it. (I know its not the best ADC, but we can make better use of its features)

Give me an idea on what you mean for the slow slope and I can probably lay it out.

Also should that also not imply R2-1/R2-2 / R1-1/R1-2 / R3-1/R3-2 should be using a resistor array to increase matching?

edit: (Moving C13 to -15V makes things a lot easier on my side, that was the only other part left possibly adding noise to the ground)
edit2: Yep, that poly is a big-one

[Kleinstein]

For C26 C28 COG caps should be OK too. Even X7R has a good chance to be good enough.  They may be even smaller than 100 nF - in theory 10 nF would be good enough, not to amplify 20 kHz. 100 nF is just convenient when using film caps anyway.

C13 should be towards the -14 V reference output , not -15 V supply.

The SMD resistor arrays linked are more like at the low end. They may still need to use the frequent gain adjustment.
Still they are definitely an option for a low cost version, and they should no be so difficult to solder. I currently have individual resistors and rather poor gain stability (well possible my resistors are outside of there 15 ppm/K specs).

I though of something like the MORN series:
https://www.mouser.de/ProductDetail/Vishay-Thin-Film/MORNTA5001AT5?qs=sGAEpiMZZMvrmc6UYKmaNaFuYzg9D8IyI2HjpkrNNLo%3D
At a little over $3 they are not that expensive and TC matching may be good enough to get away without the frequent adjustment.

AFAIK they could use the same footprint as LT5400  ( better specs, but 2.5 times the price), just without the exposed pad for improved thermals.
There is not need for accurate value matching - so the cheaper versions are sufficient.

The ADC in the 80196 used in the 34401 looks like it could be limiting performance. This is because there is no rundown phase in between and thus more contribution from the auxiliary ADC. In the 34401 the auxiliary ADC has to cover some +-1-2 µs worth of reference current. In my solution the auxiliary ADC only covers some 12 ns, and the ADC can work in hold mode. So it is much less demanding.

The 10 Bit ADC in the AVR is good enough for my version. I don't even need the full resolution - currently only some 200 LSB used, leaving plenty of head-room and tolerance for the trimmer adjustment. The ADC would be a little more critical in a version without the slow slope and thus symmetrical +-14 V reference. If the fast rundown resolution reaches some 100 ns the 10 Bit ADC should be sufficient.

Attached is the schematics for an slightly changed reference part. R19,R21 now set the slow slope. The voltage levels would be some 5% smaller, but this should not be an issue.

[Rerouter]

Schematic attached where?

I should be able to just include both the MSOP and the 0603 array footprints, looks like they fit together pretty well.

Also for the AVR you are using, don't forget that you can use the analog comparitor for any ADC pin, not sure if that helps simplify some stuff for you, but the option is there,

Edit: Resistor Network Change Over done, not that much needed to be altered, just some nudging to make it fit

[Kleinstein]

Sorry for leaving out the schematics.

R1-R3 should also be good matching. R3 is even more critical, as it can contribute to nonlinearity.
So an array for R1-R3 is probably a good idea. The alternative would be really good resistors like BMF or good wire wounds.
For a low cost version the fast gain measurement is still an option to compensate for much of the thermal effects.

The analog comparator pins are not that bad positioned. So I have no need to route the comparator through the ADC mux. This would also need to turn off the ADC. So for a very fast conversion the µC internal ADC conversion could no longer overlap the next run-up. At least in my layout the lines to the comparator are not a problem.
 
For a time I was considering an external comparator because the AVR is faster waiting for an external signal (3 cycle loop) than waiting for the internal comparator (4 cycle loop). However a 3 cycle loops also has downsides and the µC internal ADC turned out to be surprisingly accurate: The ADC readings do not scatter over much more than the range of the time step.
The accuracy of the comparator is nice but with the ADC as the next step not important.

Edit:
There is no need to adjust the asymmetry / slow slope. It is much easier to measure the slow slope and use the measured value instead of a nominal. The same is true for the reference of the µC internal ADC: the ratio relative to the main reference can be measured relatively fast.  These internal cal measurements are quite fast (some 20-200 ms). The values are also not that critical, so that an adjustment every month or maybe year  /  20 C temperature change could be enough.  Only just after turn on is not the best time.

[Rerouter]

Updated as you suggested, It does alter the output voltages closer to +13.4 and -12.2 as far as I can see, do we need to relabel the reference voltages?

And attached is more or less your schematic, but with tiny tweaks, like both op amps use +-15V and R77 is 14.3K to reduce ground current seeing as it only changes the final output by a few ppm.

Edit: For the R1 - R3 array, Is having larger values in parrellel benificial, or would a 4 resistor array be suitable, if there is a benifit would a series/parrellel arrangement for each be beneficial, e.g. 12 resistors in total.

[iMo]

Your RN201 - the pin 2 should be connected to pin 1 (not 8 ).

[Kleinstein]

The supply current for the OPs would be towards the power ground, not the signal ground. So I don't see a problem using only 15 V for one of the OPs. There is not need for balancing the current to the supply ground.

For the resistors R1-R3 using resistors in parallel / series could be an option in some cases. It very much depends on the arrays and an available values:  e.g. the LT5400 is only available in 100 K and 10K (which would be too low). 100 K should work, though 50 K would have a slight advantage with noise. So here 2 in parallel might be an option - though relatively expensive. Populating the 2 nd array is of cause optional.

With the relatively cheap and small SMD networks like ACASA, one could consider using 2 or even 3 in series (e.g. 20 K, maybe 10 K) to spread out heating and get slightly better TC matching from statistical mixing. Parallel connection would be more difficult from the layout and high value resistors may have higher excess noise (thinner film). The 4 th resistor each could in theory be used for power compensation (e.g. heating controlled via an DAC).

NOMCA resistors come with 7 or 8 resistors anyway - so a combination would be natural.

[Rerouter]

IMO can you explain your reasoning. It matches his schematic. And that first resistor does not have a steady state current like the other resistors.

For your LT5400 option what would be your preference 2x 10K in series or 3x 100K in parrellel. The 10K sounds better for thermal matching but less sure if 20K is getting to low.

[iMo]

IMO can you explain your reasoning. It matches his schematic.

Doublecheck the wiring of the first two 5k resistors wired to the IC9'th inverting input..

[iMo]

- S&H sample time is 1,33us (8 states per 167us as it runs at 12MHz) in fast mode, compared to tens us period of modulation frequency.

It could be they use the modulation patterns (see below) where the S-0 and S+0 are there for some long enough time allowing even a slow ADC to take a sample..

From HP Journal Apr 1989

[jaromir]

This got me thinking for a moment.
Actuating two switches at once can't compensate input current (from ADC input) into integrator; all you can do is cancel two strong runup sources, achieving the same effect as having both switches turned off.

[Rerouter]

Yep, My mistake, Here is the fixed one with the resistor arrays for the input resistors

[iMo]

RN202/203 - I would use 7-2 or 6-3 for the heater

[Kleinstein]

The 34401 ADc circuit does not have independent control over the positive and negative references, they both come from a single xx74 flip-flop.  Otherwise it would make sense to at least turn of the references (or use both together) when reading the ADC on the fly. This would at least reduce the slope - there is still the input signal, so only a factor 3-4 advantage in worst case.
So the 34401 has to do ADC sampling with one reference active. This would add 2 partially counting phases at the start and end of the conversion. This could be a kind of internal calibration factor, that could likely be determined from test measurements (e.g. with zero input), possibly together with the auxiliary ADC scale.

The switching scheme with both reference on or both of has pros and cons. The good thing is that the step in current to the integrator is smaller. So the transient peak at the integrator would be smaller. the negative side is having two peaks and even. In addition there is a small change to get some nonlinearity, if the two cases of getting near zero are not behaving exactly the same, e.g. due to parasitic capacitance that is different. I had a similar case, that cause noticeable linearity problems right in the center of the range:  in this range the use of both cases suddenly changes from one extreme case to the other. So even very minute differences get very visible.  Anyway this is a simple software question and thus easy to change / fix afterwords.

For the asymmetry part in the references, I start to get 2 nd thoughts about the alternative version with R19/R21: the extra divider has more effect on the difference value. So it depends if this is more attractive. If matching between R19/R21 is very good, its a good way, but in a simple form the single resistor reasonable matching the array may be easier. I think it's not clear if R19/R21 matching is more than 3 times better than R7 to R8 matching in the old case.

For the resistor quality I see mainly 2 cases:
1) really good resistors /  arrays, so that one can use infrequent gain measurement, just like used in many modern meters.
2) simpler resistors and a gain measurement for every conversion. This is slower (3 conversions instead of 2) and slightly higher noise (some extra noise effectively added to the reference).
This is a software question and one could still use the 1st. version for fast readings and the 2nd for slower ones.
Case 1 likely would need something like LT5400 or similar quality. If one accepts to use case 2 with the extra reading, the resistor TC is less important. Than the physical size of the resistors may matter, so they don't cool too fast over the 60 ms cycle. So there is slightly limited value of intermediate quality resistors. In the data-sheet of the ACASA resistor arrays I have not found noise specs. If rather poor in this aspect, it could be a deal breaker. So it may be worth a test before a final layout.

When using LT5400 for the integrator, the resistor value choice is a balance between noise and INL.  For the 3458 design they found some 300 µA reference current a good value for good INL. The 34401 uses some 330 µA. So I would prefer 100K resistors, either 1 x or 2 x in parallel. Even with 100 K resistors low noise levels (good enough for a LM399) should still be possible. I had tested an earlier ADC version (still on the bread board) with some 105 K resistors - the noise was higher, but still acceptable.

Only 2 x 10 K in series would be on the low side - lower noise, but possibly INL problems as the current steps would be higher. Maybe I should first test such high current level to see if I get visible INL problems. However INL testing is difficult and I still have some problems with switching to do the test.

The choice of the resistors is a difficult one. And good resistors (e.g. LT5400 at some $9) could easily be the most expensive parts. For a low cost version and as a 1st test one can get away with simpler resistors and the extra conversion.

For the layout, i don't think one would need that much cut outs: the LM399 temperature is about constant and thus not so problematic. Everything behind the MUX is not that sensitive to small offsets. I would more consider the option to have either the LM399 or an external reference - e.g. like in the Keysight 34465/34470.
The heat source I would be more worried about is the input buffer. So a few holes or a small cut there may be worth it.

[iMo]

What about to layout a single package 4x10k for reference and a single package for 4x100k input, with the pads shape where both LT5400 incl. thermal pad (there are two grades available afaik) and those cheaper networks in similar package would fit? That would be the simplest solution, imho.

These latest DIY designs profit from using "modern" parts (thus making the design simpler), I would not mess with single resistors there.. The final effort needed with using higher TC ratio matching parts is not worth $10 price difference.

PS: could we somehow tell what will be the "noise increase in practical measurements" when using 100k vs. 50k input resistors?

[iMo]

..It's got 10-bit ADC and integrator output is routed to one of ADC inputs, confirming this idea. This allows to omit zero comparator and slope amplifier, both being critical components to integrating ADCs..
..I wonder how many bits (or digits of result) are they getting from rundown phase..

While looking at the schematics the output of the integrator has 3 connections:
1. XADIN - via 100k directly from the buffered input stage
2. COMP - it goes to the Asic (U501-A)
3. FLASH - it goes to 80C196, Slow_10bit_ADC0

While the XADIN mixes with integrator's output aprox 1:10 I think it may work as an overload (out of range) indication and the COMParator inside the Asic could be of more comp levels (ie. a "4-8bit Flash ADC" ??).

PS: As the Asic is orchestrating the 7474 toggling (+/-refs) the flash_ADC's results inside the Asic follow the integrator's output with say ~50ns delay..
The ADC value is then made of coarse ADC in 80C196 and the Asic's flash_ADC value (could be 10-14 noise free bits in total).
The Asic has got all its Addr and Data lines wired in parallel with the 196, thus it may write the Flash_ADC results into the memory (an external 32kB sram) and the 80C196 makes some statistics to get even better results then.

PPS: the signal names "COMP" and FLASH" have been chosen by HP to mislead the competitors, it seems

[Rerouter]

Kleinstein,
For R19 / R21, 2ppm tracking ratio arrays are about $1.80 in sot23, pick a ratio that is available that suits you and its easy to route in.
e.g. https://au.mouser.com/datasheet/2/414/DIV23-1551440.pdf

My understanding is for most of these resistor arrays, the absolute value doesn't matter at all, only that there relative tracking PPM is as close to 0 as possible, lets say better than 2ppm
As such, we don't really need to lock things to the LT5400, there are tens of alternatives in similar packages that meet that specification, All the use cases are relative, not absolute, it doesn't matter that that 25K became a 25.068, so long as all 3 have, or am I inferring that incorrectly. even your recent respin lets us lock down a fixed ration with R19/R21 instead of R8 being a mystery on the old one.

E.g. for the input resistors, we can use another morna array at 2ppm tracking for a 25K input resistance, I know its not the <1ppm of the LT5400, but in reality I feel it should be sufficient, and leaves us alternatives with higher values in the same series.
https://au.mouser.com/datasheet/2/427/morn-795262.pdf

You mentioned an external reference input, plan out the circuit and I can route it,

And finally added some more tabs to make it a bit more rigid, I was more trying to prevent board flex from upsetting the reference,

IMO, flipped around your resistor, now do we want to run current to heat that resistor, and how do you plan to implement it, or do we just use it to measure that resistor, e.g. use the second amp of the MCP6002 to measure the current from the positive reference and amplify it to an ADC or similar.

Edit: Is it not easier to measure the temperature of the array to better than 1C? this seems like it could be the easiest solution, then pulse some power every few seconds to hold it there. I can place an SMD NTC right next to it.

[iMo]

I think you must have some Temperature feedback to keep the temp constant. As I wrote above I was thinking to use the thermal pad as the point where to thermally couple an NTC or a diode.
The big Q is whether it is needed with LTC5400 and its 0.2ppm/K ratio matching TC..

[jaromir]

While looking at the schematics the output of the integrator has 3 connections:
1. XADIN - via 100k directly from the buffered input stage
2. COMP - it goes to the Asic (U501-A)
3. FLASH - it goes to 80C196, Slow_10bit_ADC0

While the XADIN mixes with integrator's output aprox 1:10 I think it may work as an overload (out of range) indication and the COMParator inside the Asic could be of more comp levels (ie. a "4-8bit Flash ADC" ??).

PS: As the Asic is orchestrating the 7474 toggling (+/-refs) the flash_ADC's results inside the Asic follow the integrator's output with say ~50ns delay..
The ADC value is then made of coarse ADC in 80C196 and the Asic's flash_ADC value (could be 10-14 noise free bits in total).
The Asic has got all its Addr and Data lines wired in parallel with the 196, thus it may write the Flash_ADC results into the memory (an external 32kB sram) and the 80C196 makes some statistics to get even better results then.

PPS: the signal names "COMP" and FLASH" have been chosen by HP to mislead the competitors, it seems

XADIN is the same as ADIN, but has reverse polarity (not just buffered signal) and is amplified roughly 1,2x.
COMP is mixture of those two signals 1:12.
I have no idea what is the deal here.

The only IC that really receives the output of integrator is 80C196.

Stitching together results of slow ADC in 80196 and fast ADC in ASIC (we have no idea, if there is really one) IMHO brings more problems than it solves, especially on fast moving target, as is the output voltage of integrator. With +-4LSB INL of slow ADC there is no way of getting reasonable 10 bits, let alone 14 bits.
Since we are speculating, I don't believe there is much more involved analog circuitry inside the ASIC than one or few analog comparators or opamps. There is no reference going inside the ASIC (though the reference goes to 80C196) and whole ASIC is fed by "dirty" 5V rail. COMP pin is sitting between two digital outputs. I can't imagine how would anybody place ADC in here.

[Kleinstein]

The noise from the integrator resistors is one of the larger components, but not the only noise source. Currently I get an effective noise level for a single conversion of about 60 nV/Sqrt(Hz) with 25 K resistors. With 50 K (but also a few other small changes) I had down to some 70 nv/Sqrt(Hz). This corresponds to the noise of a 220 K receptively 300 K resistors. The simple resistor noise should contribute twice the resistor value as a noise source. So 50 K rep. 100 K of this were due to the resistors. With 3x100 K resistors the expected noise would at about a 450 K equivalent and thus around 85 nV/sqrt(Hz).  This is still very good and normally considered worth 8.5 digits, if the reference is good. I have not yet tested 100 K on the PCB - but it did work with the breadboard version and +-7 V reference.

Jaromirs configuration with 200 K for the input and 2x100K for the reference should contribute like a 600 K resistor (200K + 2x200K). The big downside there is the 200 K for the input and less for the reference.  Just going to 3 x 100 K and thus a slightly reduced range (e.g. +-12 V  ? instead of +-14 V limited by the buffer) should reduce the noise quite a bit.

So I think a single MSOP foot print with thermal pad for the LT5400 (100K) should be OK. This would also fit (just ignore the thermal pad) a lower cost MORN - 50 K array.  Fitting the ASAZA (0612) size array would likely be borderline and tricky, as it is smaller and different pitch.
A second food-print is parallel is likely tricky from the layout, though possible (e.g. other side of the board).

In both cases the lower precision version should be sufficient - I see little need for much better than 0.5% matching of the resistor values.

For the ASAZA SMD arrays, I would consider using 2 x 20 K in series, but to be sure it may need a noise test up-front.

TC matching at the integrator is for 2 reasons:  gain drift and INL due to self heating. Gain drift is essentially directly set by the TC matching of the resistors. There is a part from the reference amplification and a part from the integrator. Comparing with other DMMs,  I would consider 2 ppm/K acceptable and 5 ppm/K (like with the ASAZA) would be more like on the lower end of the 6 digit DMMs. The INL part depends on the self heating: with these small chips even 100 K cause quite some temperature rise. 100 µA at 10 V give 1 mW and thus some 0.1 ... 0.5 K of temperature rise. With 5 ppm/K this would cause a 0.5...2.5  ppm of INL error. The self heating part could in theory be compensated by applying an additional voltage to the 4 the resistor to keep the total chip power approximately constant. The voltage could come from a small e.g. 8 bit DAC controlled from the last ADC result. So it would not be temperature regulation but a calculated power compensation.

The other mitigating option is measuring the gain more often. This also includes the thermal INL effect as the temperature change is usually slow. With the very low noise ADC to start with this is less of a disadvantage than it was in the K19x and similar meters in the old days.

Without the frequent gain measurement it makes sense to aim for <1 ppm/K range TC matching. With less perfect TC matching I would consider that either power compensation or the frequent gain measurement would be a good idea.
With the 0.2 ppm/K matching of the LT5400 should not need power compensation - due to the 100 K resistance the power is low anyway.

The other positive point about the LT5400 is that it has specified <-45 db current (flicker) noise while the other arrays often only give < -30 dB  (actual noise could still be better, depending on resistor value). Form my estimates a -30dB noise level could already be noticeable.


For the 34401 configuration: the   XADIN path goes to the inverted input signal. HP used this in some DMMs to reduce the effect of dielectric absorption. So the comparator signal is no longer suitable for an ADC in the ASIC.
My guess is that they called the ADC signal flash, as they may initially have planed with an flash ADC and later changed to the 80196 internal one.

By adding the inverted input signal to the comparator signal, the average integrator output changes less with the applied input voltage. The average integrator voltage is an important factor to set the effect of long time scale dielectric absorption. So keeping this more constant could reduce DA related errors.

However the extra part from the input signal only compensates for the linear part - so the DA part that is avoided is just a small contribution to gain, not INL. Though likely not helping with INL as intended, it still has a positive effect: it reduces the swing and thus allows for a smaller integrator cap and thus less noise for very short conversions and a smaller range for the µC internal ADC.

In my case, I decides against a similar part, as the slope amplifier is shared for the comparator and residual charge ADC. A second comparator for run-up is probably causing more problems than good.

[Rerouter]

0612 arrays are easy to add with the MSOP8, It just conflicts with the option of a thermal pad, as such I may run them under but leave the traces coated, if someone wants to use the 0612 array, then they can just scratch back the solder mask a little.

I can just throw a zone fill under the resistor array to add some thermal mass to it if it really must stay as constant as possible, 24 vias and a plane make for a lot of mass for components on this scale.

[iMo]

Another question still floating around - do we really need the composite integrator? Is an OPA140 (for example) not enough?