Multilevel Inverter

[Siddhat]

So I ran into a problem while designing a five level multilevel inverter. Let me explain what I did. First of all, I simulated a three level inverter using an H-bridge circuit in LTspice and the waveforms were obtained as desired which is shown in the attached image (See file: Three_Level_Waevform). Then, the H-bridges were cascaded (connected in series) and the timings for the mosfets were calculated. But when I simulated the circuit, the output waveform is not obtained as required. Here is the circuit that were used and the waveforms that were obtained (See files: Five_Level, Five_Level_Waveform).
What is the reason for the problem in five level inverter. How can this be solved?
Thank you.

[Slh]

You need your gate drive signals to be referenced to the source of the MOSFETs that you're trying to switch. In1 and in2 are referenced to the simulation ground but the MOSFETs drain voltage depends on the state of the other h-bridge.

[Siddhat]

You need your gate drive signals to be referenced to the source of the MOSFETs that you're trying to switch. In1 and in2 are referenced to the simulation ground but the MOSFETs drain voltage depends on the state of the other h-bridge.

You're saying that the MOSFETS U1 and U2 have their gate driving signals w.r.t source but for MOSFETS U3 and U4, the gate signals are referenced to ground. But even if in1 and in2 are referenced to G1, the output is not obtained as desired. Can you explain in a bit detail?

[T3sl4co1l]

Like this.

Tim

[Siddhat]

Thank you for the answer. The circuit worked flawless in simulation.
But how is this implemented in hardware? I mean: if I use a microcontroller like the Arduino UNO to generate the signals in1 and in2, they are referenced to ground of Arduino which is common to system ground most of the times. But How can the gate driving signals in1 and in2 be given to the upper H-bridge such that the signals are referenced to G1? Any ideas on this?
How can a gate driving signal which is referenced to ground (say generated from an Arduino UNO) be converted to a signal so that the signal can be referenced to any node in the circuit as desired?

[T3sl4co1l]

Isolated gate drivers!

The bottom level can be common-ground (though there may still be reasons not to), and the high side can be bootstrapped, but the flying stages all need isolation -- or at least enough CM range to handle the output from the first stage.  (Or do the same thing over again, i.e. low side + high side bootstrapped drivers, common to the flying ground, then deliver the signals with digital isolators.)

In contexts where these inverters are important (high power), you'll normally use all isolated drivers, for convenience and delay matching.  The controller can be at earth or SELV reference, while the inverters are running at, whatever, 480V, 3.3kV, etc. with hazardous voltages all around.  It's also a common feature to provide a feedback signal on these gate drivers: desat detection, as a last resort overcurrent protection feature.

An Arduino will certainly NOT be used for control... but on a small scale (like 12V supply and lab demos) this is an okay way to study it.

Tim

[Siddhat]

I researched into isolated gate drivers and found that optocouplers could do the work. I used an optocoupler as shown in figure and simulated the circuit. But the output waveform was not obtained as required. See the image below. Any ideas what could be happening and how could this be solved? (Vcc1 is referenced to G1)

[T3sl4co1l]

Vcc1 ground moved over as shown?

No current limiting resistor to the LED?

Check the capacitance and switching speed of the opto.  More likely you'll want a SFH6345 (discrete opto, with good enough speed and immunity), 6N137 (opto, digital output); or a digital isolator like by AD, Texas Instruments or Silicon Labs (or others?) -- these are ICs with integrated transformers or capacitors, driven in such a way that, as tiny as they are, signals can be coupled between sides, at excellent isolation voltage and immunity.

Tim

[Siddhat]

Yes, the optocoupler did the work. I even managed to simulate a seven level multi level inverter. See the beautiful waveform in the image. And with this I could possibly simulate nine, eleven, and so on levels of multi level inverter. For now, the circuit is implemented on a breadboard for demonstration purposes only.
But what considerations should I take when using this for high power applications and the design guidelines?

[TheMG]

But what considerations should I take when using this for high power applications and the design guidelines?

How much power are we talking about? From what information I can find on the subject, such multilevel inverter configurations are gaining popularity and have advantages for BIG power applications, such as bringing DC power from renewable energy sources to the AC power grid, at voltages of several kilovolts and powers of hundreds of kW to multiple MW.

As far as I can gather, the main advantage is the ability to invert high voltages directly as each semiconductor switch (IGBT usually) doesn't have to handle the full voltage, it only handles a fraction of the total voltage depending on the number of levels (someone let me know if I'm wrong), as opposed to lower voltages at higher currents then going to a step-up transformer, which adds both expense and energy losses.

For smaller inverters, say 240VAC at a few kW, I don't really see any significant advantage. For that it would make more sense to use a simple PWM inverter which would yield very nice sinusoidal waveforms without all the extra parts and complexity of a multi-level inverter in a small scale application. Even multi-level inverters will often have PWM added to further reduce harmonics, further complicating the gate drive scheme, which would be better handled by a DSP than a simple microcontroller such as Arduino, as you need to also consider the need to have fast responsive feedback to reduce waveform distortions due to changes in loads and non-linear loads.

[T3sl4co1l]

Well, keep in mind -- at those power levels (some kW and up), strays (parasitics) matter.  You cannot design an inverter without mitigating these effects.  Remember that every wire/trace is inductance, of ballpark 1nH/mm.  Less when wider (broad-facing arrangement) and closely spaced, or vice versa.  It adds up, especially at high currents, fast rate of change, and large builds (e.g. IGBT modules vs. THT vs. SMT components).  Which is part of the reason why larger converters simply can't run as fast.  (Another part being, high voltage devices just don't switch as fast, either.  The 3kV+ IGBTs usually take a few microseconds.)  Understand what (stray) inductances and (device or other) capacitances are important, during which phases of the switching cycle.

This isn't an easy subject, it can take years of practice; be patient.  Do smaller tests first, see how it works, make an intentionally bad circuit, add snubbers to fix it, etc.

I think the biggest problem with the type of multilevel inverter shown, is that each bridge needs an isolated supply, well enough isolated that it doesn't load down the switching edge from the proceeding stage.  This is not easy to do; a typical isolation transformer of some kVA to MVA capacity, will have at least 10s of pF, up to some nF, of stray capacitance between the winding and the primary or core.  And you will rarely if ever have isolated supplies handy; they must be isolated with an additional DC-DC converter stage, nearly doubling the complexity of the system -- and costing precious efficiency.

Tim