Using 4046-Type PLLs Successfully

[C]

Might think of a passive filter network that does more the just make steady output.
You have steady when in narrow working range.
You could have rate of change creating a forward feedback & a negative feed back that when in narrow working range cancel.

[G0HZU]

G0HZU also mentions a "'post PFD' current sink/source circuit". Unfortunately, the 4046 is not suited for charge-pump operation, having only one (three-state) output and so we are left with the active loop controller/filter.

Yes, I should have made it clearer that I applied the sink source circuit to a similar phase detector found in Motorola PLL chips and these have V and R PD outputs. I also dabbled with the Plessey range of PLL chips that used a PFD and a sample/hold phase detector together as a coarse and fine PD. The aim was to get better reference sideband rejection once locked. But the Plessey parts weren't suitable as the lock time was compromised too much with the dual PD operation.

I entered your example data into an old excel spreadsheet for the 4046 type PFD. See below. This obviously wasn't the tool I used back in 1990 and everything was DOS based back in those days. I think I only used the excel spreadsheet once or twice for revision purposes but it seems to agree with your paper. I can't remember where the equations or pictures came from. Probably Gardner.

[Benta]

G0HZU, interesting. Independent verification is always nice.
Thank You for sharing.

[sourcecharge]

I've got a question to all you professional electronics engineers...

The analog PLL really is limited by the VCO.

Has anyone made a digital VCO?

Not a DCO, but a VCO that was programed by a DC voltage input accurate to the micro-volt.

Seems simple enough, but I have not done DCOs, DACs, FPGAs, Microprocessors, etc, etc...

If a digital VCO was made that could have a linear micro-voltage to frequency sweep of like, (1,000,000 : 1), the PLL would be propelled forward to having almost an instantaneous, unbreakable lock, with no jitter using active filters.

The only problem with active filters that I found was that even though they decrease the lock in time and create less jitter, the range of the PLL lock in is greatly decreased.

Just a thought...

BTW, I actually did alot of research on digital frequency multiplication, forgot what I was going to use it for...

If anyone is interested, make a thread and post what you got already, and maybe I can help.