CPLD for PLL prescaller

[ealex]

Hello

I've created a small verilog implementation for a PLL prescaler:
The design contains:
 - 2 x 32 bit divide by N
 - 2 x inputs for Frequency and reference input
 - 2 x outputs for divided clock, the maximum Fout is Fin / 2
 - 2 x 32 bit shift registers for loading data, each with it's own input line
 - 1 x serial load clock
 - 1 x serial chip select, the shifted values are applied on the rising edge.

The divide by N counters are clocked by the input signal  that needs to be divided - i don't know if it's a good idea but it worked.

The design fits on an LCMX02-256HC-6SG32I lattice CPLD, in 32 pin qfn package and it's specified to work up to 150Mhz.

I've already tested it on a bigger device and it seems to work properly - the ratio between programmed value and input / output clocks, data loading and no glitches.

Can this be used in real life ? the ideea is to create a generic sealed "pll block" that contains only the prescalers and phase comparator.
For the phase comparator I intend to use a HC4046. Can it be implemented it in the CPLD as well ? It seems there is some room left.

I'm quite curios of how many design "rules" I've overlooked as I'm trying to learn verilog by myself.

I've attached the design files and reports.