Ok, I've done a few timing simulations. After experimenting around, there was only 1 way to get consistent clean output results. Negative edge clock was not used. All that was needed was the 'ALTDDIO_IN' megafunction for the sync input. This function automatically sets up a bunch of hidden timing corrections to some internal registers so the the sync in is captured on the rising and falling edge of the 336MHz clock, however, the results of the previous negative edge capture are delayed and are presented on the positive edge of the next clock. Basically it has 1 input, 2 outputs, dataout_h, dataout_l.
Here is the simulation I came up with.
Note that 'clk_outa' is what feeds the input of the second PLL.
Output 'clk_fix' is a test output for visualization of the internal counter generating th 10.5MHz clock.
Notice what happens to 'clk_outa' when I shift the falling edge of 'SYNC_IN' by half a 336MHz clock at a time.
Now, because you are operating with a DDR input sampling at 672MHz when the theoretical limit is 500MHz, there were some things I had to set in Quartus to get reliable results. It doesn't matter what your reported FMAX is, the outputs get skewed and the input sampling phase timing isn't as reliable without these changes.
In assignment settings, compiler settings:
1. Choose Speed or Performance, not Balanced or anything with 'Area' in the settings.
2. Do not prevent register retiming. It is needed for the DDR input.
3. In advanced settings, make sure 'Power Optimization During Synthesis' is turned off.
4. In Fitter advanced settings, make sure 'Power Optimization During Fitting' is turned off.
In the project's pinout:
1. At minimum, your SYNC_IN should be on a DDR_DQ IO pin on a high speed IO bank. (If I remember correctly, the top & bottom IO banks are high speed and left and right side ones are slower, however, this is on BGA I don't know about QFP)
2. It is preferable that your 10.5MHz clock output is in the same IO bank.
This will make your design run as fast as possible. Not that it's going any faster than 336MHz, but the IO pin timing will be tight enough that you will capture that half-clock cycle SYNC_IN with high enough quality phase that it will inprove your PLLs overall jitter.
Here is the System verilog code I wrote to generate the output:
module MITI_PLL_Divider (
input logic clk,
input logic sync_inh,
input logic sync_inl,
output logic clk_out,
output logic clk_fix
);
logic [5:0] counter, counter_dl;
logic sync_inh_reg, sync_inl_reg;
always_ff @(posedge clk) begin
sync_inh_reg <= sync_inh;
counter_dl <= counter;
clk_out <= (counter_dl[5] && sync_inl_reg) ? counter_dl[4] : counter[4];
clk_fix <= counter[4];
if (!sync_inh && sync_inh_reg) begin
counter <= 0;
sync_inl_reg <= sync_inl;
end else counter <= counter +1;
end // @posedge clk
endmodule