Yes, really close, except 420MHz is overkill while 210MHz will do and since it is a short input counter section, you will not have any trouble with the FMAX on the slowest cyclone. Even 420 might work, but this is not how you do this if you want an easy sample pixel clock source. There are a few minor tricks to get a few controls and optional second PLL to get this to work the way you want.
Item #1, is the pixel sample clock actually 10.5MHz on the dot, or 21MHz on the dot?
Item #2, you need to know how many clock 10.5/21MHz cycles it is from H-Sync to H-Sync, not how many pixels are on the screen. It is also important to know if this is an odd number. I've writen the rest assuming it is an even number.
Next, if 21MHz is the right figure, choose a core clock frequency 16x this figure:
This means make 1 PLL in the cyclone 336MHz from your 25/50MHz source.
Make a sync UP counter with sync reset (not async) with 6 bits.
Next for the sync input.
First make that registered.
Then with a second clk delay register, make a falling edge transition detector which will be the reset for your counter.
Note that at stage 2 in developement, you will want to make this reset a selectable/programmable pipe delay of 1 to 32 clock cycles as this will adjust the sample phase of you pixel sampling period so you may grab pixels on the center sweet spot.
Next, make a registered output tied to bit 4 (starting at bit 0) of this counter.
This output will contain your new 10.5MHz clock.
If Your H-Sync pixel clock divides into 4, use bit 5 for a reference 5.25 MHz clock, otherwise you may need to switch to 10.5MHz on bit 4.
In Quartus, just tie bit 5, 5.25MHz into a second 1:4 PLL to generate a new system 21MHz with a 'low bandwidth' setting.
That 'low bandwidth' setting slows down the Cyclone's PLL phase alignment to below 1 MHz smoothing out that potential +/- 2ns glitch once every few H-Syncs. That's your new pixel sampling clock. (Make it a 1:2 if the true pixel sampling is only 10.5MHz)
If you have any HDL troubles, or some added features to remove H-Sync noise, or transfer sampled data between clock domains, make a new thread in the 'FPGA' section of this forum. Note I can only really help with Verilog or System Verilog or Quartus block diagram entry.
Looking at you current scope PLL jitter snapshot, this solution directly outputting bit 3 or 4 of you counter should reveal a 10.5/21MHz clock with +/-1.5ns jitter around the H-sync if any at all. Unless your scope crystal clock is junk, this should roast your current PLL scope shots.
Outputting the second PLL from the cyclone with the low bandwidth setting generated from that clock would have a smoothed out effect.
As for the screen you are driving. There usually is enough play to operate it from a fairly clean multiple of the 10.5MHz clock, but, the cyclone's pll is quite capable of doing simultaneous fractional outputs from 1 PLL, so it can easily make the 55.125 along the filtered 10.5MHz or 21MHz clock, or even all 3 clocks.