MII management in (SPI-managed) switch MAC to PHY connection

[helge]

I'm currently doing my first 10/100 ethernet project that involves a Micrel KSZ8873-MLLJ 3-port switch and I am having difficulty understanding what happens to the MDC/MDIO lines.
These are supposed to form a two-wire serial bus through which a station management entity (the ethernet MAC) configures the PHY device. Unfortunately, the KSZ8873 serial pins have multiple functions from which one is selected at start-up from strap-ins.

As far as I understand the scant instructions from the manual, selecting SPI interface tri-states the SPI pins when SS is high - and these also dub as the MDIO/MDC pins. How does the PHY get configured then? 

Both Micrel applications notes and third-party manuals/application notes don't seem to waste time on this minor annoyance.

I found the following documents quite helpful to get a basic understanding of what I am dealing with:
http://ww1.microchip.com/downloads/en/AppNotes/01120a.pdf
http://www.micrel.com/_PDF/Ethernet/White%20Paper/Ethernet_to_processors.pdf

Still I have no clue what will happen when I build a circuit with, say, an AVR microcontroller that'll act as SPI master on the bus with the switch MAC and some PHY device.
By the way, I need this arrangement because I have to interface with a powerline communication module that expresses a MAC/ PHY-mode MII interface. Thanks for the help!

[AndyC_772]

Sounds like SS is the chip select, which identifies when this particular device is the one which should respond to signals on the other SPI pins. Drive it low at the start of your SPI bus access, and high when the transfer is complete.

[helge]

Ah, I seem to have failed to point out the major issue here:

The standard configuration goes as follows: A PHY device is supposed to be configured by the MAC via the MII (media independent interface).  (see MII management)
This requires two signal lines that form a two-wire serial bus: MDC and MDIO.

So irrespective of that the MAC looks like, things like duplex mode, 10/100 speed selection and auto-negotiation options are configured via this interface.
Looking at it from the switch as the owner of the ethernet MAC, this interface should be accessible no matter what means of switch management are employed.

Now that bloody switch chip is
1) supposed to send configuration data to a PHY device as part of the MII interface via MDC/MDIO
2) at the same time configurable through SPI that shares the same I/Os?

I don't see how that would work because for 1) to happen the MDC/MDIO lines must operate as a TWI with the switch chip being the master device and for 2) the KSZ8873 has to shut up an receive commands as a slave SPI device.

Is the SPI only usable when the switch chip is in reset state (which it has to be for initial configuration but not necessarily for management afterwards)? If not, do I have to manage the third PHY myself?

[helge]

Update: I've come to the conclusion that the switch chip only controls the internal PHYs. The MII interface has its own strapping options (speed, flow control and full/half duplex) so hard wiring both switch and external PHY will do the trick - no need for MDIO/MDC interfacing.
I won't be able to change the MII stuff afterwards but since no magnetics and line termination is involved, hard wiring for 100mbit MII won't waste too much power.
The KSZ8873 will initialize from the strap-in values. Afterwards changes through SPI are still possible. 10/100 and Auto MDI-X on/off will still be accessible while the switch is operating. Now I'll just have to prototype this .... design rules for 125 MHz differential signalling look scary...

[Ajith]

Hi can any one provide me a interface driver(SPI) to do this , interfacing 8863 switch 3 port to our microcontroller , im new to this want to learn how interfacing is done

[helge]

Hi can any one provide me a interface driver(SPI) to do this , interfacing 8863 switch 3 port to our microcontroller , im new to this want to learn how interfacing is done

Still working on it. Try getting any SPI peripheral library of your choice to work (what microcontroller are you using?). We'll then have to work our way through the Micrel documentation to figure out how to write and read data.

[MarkL]

Try taking a look at some of the utilities on Micrel's web site for the KSZ8873-MLL:

http://micrel.com/index.php/en/products/lan-solutions/switches/article/4-ksz8873mll.html

They are under "Software Package/Kit" --> "Device Drivers" on the right-hand side.

In particular, look at "kscli-20130108.tar".  This is the source code for a CLI to control the operation of the chip through the SPI port.  You can use the CLI to play with the chip to get it to operate the way you want, and then examine the source to see what you need to copy to do it in your code with your own processor.

If you haven't made it that far and are stuck on low-level SPI issues, it might be enlightening to look at their reference design (under "Eval Boards or Kit").

[helge]

now that the board is laid out allow me to do a quick follow-up with a schematic for the KSZ8873.

[Scrts]

The MII interface does no configuration at all. The PHY is configured using MDIO interface or, in your case, using SPI interface. I would go for MDIO or I2C instead of SPI. Remember to route interrupt output to your microcontroller - you will really need this!

[helge]

Thanks for pointing out the interrupt issue. As of now, both switch and the attached PHY device should configure on power-up according to their pull-up / pull-down configuration and the entire switch module should run stand-alone. For the first iteration it'll suffice to resistor encode 10Base-T or 100Base-TX.

There is a TMP101 temperature sensor next to the step down converter. Reverting to 10MBit/s operation will be considered a lower power fall-back option in case of high board temperatures. I'll have to peruse the datasheets to figure out there the traps are but right now it seems that I'll have to pump some 200 register values into the switch chip and issue a few commands to the PHY device to completely reconfigure the setup. No MDC/MDIO connection between switch and PHY exists.

[helge]

And it's done! Just two little errors later I'm running the MII at 25 MHz (full MII, 100BT). Changing the configuration will have to be done via SMI (MDIO/MDC) for the PHY and SPI for the switch device. A comprehensive summary of PHY registers can be found in the IP101 datasheet (the original 802 specs don't seem to be available for free download? ). Only three things remain to be done:

- read PHY link status via SMI, issue a reset via SMI if no-link timeout is reached
- set switch MAC and external PHY MII speed via SPI / SMI to reduce power consumption if required
- motivate onboard µC to allow config changes and status messages via UART (link status, MII speed, reset, board temperature)

[ajmorris]

Hi there,

Apologies for reviving an old thread, but was hoping to acquire assistance with this chip, similar to desired usage of the previous posters of this thread. Basically I am trying to achieve MII connection from an MCU to the KSZ8873, and send ethernet data over this connection without the use of I2C or SPI. The datasheet eludes to this being possible, but the more i attempt it, the more it seems that i2c/spi is required for configuration.
The KSZ8873 is in PHY mode, connected to the MAC configured on the MCU - i can configure the MMFR over the MDIO pin, and can see switch functionality based on these changes. Data can then be seen on an oscilloscope transmitting over the MII TX lines, but the PHY does nothing with the data.
Any help would be greatly appreciated.

Cheers

[helge]

ajmorris I thought I were the only one with such problems.

First of all (just in case you missed it) the MLLJ (extended temperature range, 100% tested "deluxe" version) datasheet is a little more refined than the MLLI one: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ8873MLLJ.pdf

As for your in-depth question please give me a day or two to look into it. My having a working KSZ8873-as-MAC version should give us a good starting point to work things out.

[ajmorris]

Hi helge, I made progress to an extent... I have discarded the idea of MMFR configuration for now, and am using I2C to configure it to the settings i want. As a result, my TX is now working with MII data from my mcu to the KSZ8873 is PHY mode. RX however is not. It appears to be a clocking issue, in that there is nothing coming out of the rxclk pin from the KSZ8873 (which there should be). I can bridge tx and rx clks together in the same way that my mcu works on its dev board, however this breaks tx. Did you have any clocking issues over the MII interface?

[helge]

Sorry I lost track of the thread.
In my design there are 33R resistor arrays and single resistors for signal integrity / inline termination (see http://electronics.stackexchange.com/questions/7709/why-put-a-resistor-in-series-with-signal-line ).

The PHY should provide both RX and TX clocks while the MAC can provide a reference clock to the PHY (like an external oscillator).

To start out I made use of the pull-up/pull-down configuration straps to get a working condition without the added complexity of the management interface (maybe you accidentally generated a LO/HI condition somewhere on startup?). I've attached the relevant schematic sections for KSZ8873 in MAC mode. That's the inverse of what you need but I hope it helps to some extent.

Btw. see ds p.32 regarding the missing PHY MRXER / MTXER signals.