1. Why are the buffer and PHY specified to use LVPECL differential signalling and at the same time specify common mode voltages which are much below 2 V. As far as I know, the LVPECL standard uses a common mode voltage of 2V.
Let's see if I can answer this question for you. It may help to understand a bit of where LVPECL, PECL, etc. came from. LVPECL, PECL are all simply variations of ECL that operate from a positive supply instead of a negative supply like ECL did. ECL (Emitter Coupled Logic) is based on emitter-coupled-pairs, or differential pairs, also known as long-tailed pairs. Basically a differential amplifier - a pair of NPN transistors with their emitters connected together to a current source. The base connections are the inputs. A resistor is connected from each collector to the upper supply rail (traditionally ground for ECL). A pair of common-collector (emitter follower) transistors are connected to the collectors of the diff-pair, and the output is taken directly from the emitters of these emitter follower transistors.
From this description, it is clear that the logic levels are referenced to the upper supply rail. This is why ECL used a negative supply (usually -5.2V to 10K and 10KH logic, and -4.5V for the faster 100K logic) - so that the logic reference was ground (stable, good return path, etc.). Since nearly every other logic family used a positive supply, folks started using standard ECL circuits on a positive supply, and called it PECL (for Positive ECL). Still works, but you just have to take care about very careful layout and bypassing of the positive power supply. Later, folks started producing families specifically designed for PECL operation (5V typ), and then later for LVPECL (3.3V typ).
In any case, the logic levels for PECL are still referenced to the positive supply. When the diff-pair is fully switched in one direction, all of the tail current is going through one of the collector resistors, and virtually none through the other. Typically, the maximum voltage drop across one of the collector resistors was about 0.9 to 1V. Since the collector voltages were buffered to the output by emitter followers, the logic voltages were simply one Vbe drop below the collector voltages internally. A logic "high" was VCC-0.8V or so, and a logic low was VCC-1 -0.7V or so. Why would the Vbe drop be lower in the logic low case? - Because the emitter follower isn't loaded as heavy.
Since the outputs were effectively open emitters, they needed a pulldown resistor to be properly biased. Also, since the edge speed of ECL/PECL/etc. was very fast, the lines were typically done as 50 ohm lines, thus needed 50 ohm terminations. However, a 50 ohm resistor to the negative supply would draw *way* too much current - so the traditional termination was 50 ohms to -2V (2V below the positive supply rail). This ensured that the emitter followers were still properly biased (sourcing current) during a logic low, and not overloaded when driving a logic high. This was often done with a split termination - a pair of resistors that provided the Thevenin equivalent to 50 ohms to VCC-2V.
I guess the last statement would be - don't confuse the common mode voltage with the termination voltage. Common mode voltage is the voltage midway between the logic high and low levels. The termination voltage is the reference point that the termination resistors go to, which in the case of any ECL like output, is just slightly below the logic low level.