LVPECL clock buffer output termination

[mairomaster]

Hi guys,

I am working on a reasonably complex board with many different components - CPUs, FPGAs, a bunch of interfaces, etc. I have a few copies of the board manufactured and I have been testing them in the past 2 weeks. All modules/interfaces seem to work fine so far but there is a problem.

I am using a 10G PHY connected to an FPGA for 10G networking. The PHY didn't seem to work at all and eventually I found that the problem is the common mode voltage level of the reference clock supplied to it.

Here is a description of my system:

The reference clock of the PHY is 156.25 MHz and is supplied by a LVPECL differential clock buffer.
For the clock buffer I use Silicon Labs 53306 with 2.5V supply voltage:
http://www.mouser.com/ds/2/368/Si53306-258663.pdf

The buffer is configured to work in LVPECL output mode, as the input of the PHY requires. In such mode the common mode voltage at the output should be 0.9 - 1.25 V (page 5 of the datasheet).

One of the outputs of the buffer is directly connected to the input of the PHY, without any termination. The PHY is supplied by multiple filtered power nets, each of them running at 1.2 V. In the PHY the two signals in the clock differential pair are internally terminated with 2 50ohm resistors to  a termination voltage of 0.8 V, generated by a voltage divider (see attached image). The common mode voltage at the input of the PHY by specifications is supposed to be between 0.7 V and 0.95 V.

With the described configuration the PHY would not work. The common mode voltage at the input was measured to be about 2.1 V (across all boards), which supposedly saturates the clock input stage. I tried to AC couple the input and add 2 90ohm DC coupling resistors to ground at the outputs of the buffer (datasheet page 15) and the PHY started working right away. In this case the common mode voltage at the input of the PHY is 0.8V (properly set by the bias circuit) and the common mode at the output of the buffer is 1.2 V.

I have a couple of questions regarding the initial problem:

1. Why are the buffer and PHY specified to use LVPECL differential signalling and at the same time specify common mode voltages which are much below 2 V. As far as I know, the LVPECL standard uses a common mode voltage of 2V.
2. Direct DC coupling is one of the allowed termination schemes for the buffer (Scheme 2, page 15). Why am I getting 2.1 V common mode voltage at the output of the buffer if by specifications it should be 0.9 - 1.25 V? Isn't the 0.8V bias voltage in the PHY supposed to correct that?

Thanks.
 

[dmills]

LVPECL uses a termination to VCC MINUS 2V, not at all the same thing as termination to 2V.
Look at the common mode termination impedance in the PHY, it is way too high to serve as a current sink for the PECL drivers (12K || 24K).
I would be thinking AC couple into the PHY and add 195 ohm resistive pull down to ground on each line at the transmitter to provide a load for the driver emitters.

Micrel have a good datasheet on termination schemes here http://www.micrel.com/_PDF/HBW/App-Notes/termination.pdf

Regards, Dan.

[mairomaster]

I noticed that a termination voltage of (Vcc-2) is commonly used with LVPECL in all sorts of datasheet/documents. However I could not find a document which explains well the whole situation and why exactly (Vcc-2) should be used. Also under which conditions this termination voltage is suitable? What happens if different supply voltages are used for the transmitter and receiver and when the receiver's supply voltage is under 2 V (my case for example)?

What are the standard LVPECL drivers current sink requirements?

Also I am still looking for an answer of question 1 in my initial post.

Thanks

[uncle_bob]

I noticed that a termination voltage of (Vcc-2) is commonly used with LVPECL in all sorts of datasheet/documents. However I could not find a document which explains well the whole situation and why exactly (Vcc-2) should be used. Also under which conditions this termination voltage is suitable? What happens if different supply voltages are used for the transmitter and receiver and when the receiver's supply voltage is under 2 V (my case for example)?

What are the standard LVPECL drivers current sink requirements?

Also I am still looking for an answer of question 1 in my initial post.

Thanks

Hi

The most basic answer to your first question is that there is no standard definition for LVPECL. PECL logic (all of it) is referenced to the supply pin on the part when run off of a positive supply. If you run one chip on 3.3, another on 5.0 and a third on 2.5, they will not talk to each other if wired directly. There is another layer past this concerning voltage coefficients and different families. That applies to all ECL, and has for as long as the stuff has been around. There is also the little note on most FPGA's about "pseudo PECL" down on page 2,587 in the doc's ...

The answer on a clock signal is quite simple:

Bias up both outputs of the transmitter with whatever you are using.
AC couple the two outputs to two inputs on the receiver side.
Bias the receiver inputs up so they are in a region they like.

If you look at the way the "big guys" do it, this is done all the time.

Bob

[dmills]

Yea, PECL tends to be all over the map, still could be worse, it could be ECL complete with negative supply voltages, nope, don't miss it, not even a little....

Do also watch the differential voltage level requirements on FPGAs, they are sometimes gratuitously incompatible with **ANYTHING** that looks like PECL without needing both caps and pads.

The reason the high speed converter types love it for clocks is mostly down to the very small additive jitter that is achievable. 

Regards, Dan.

[w2aew]

1. Why are the buffer and PHY specified to use LVPECL differential signalling and at the same time specify common mode voltages which are much below 2 V. As far as I know, the LVPECL standard uses a common mode voltage of 2V.

Let's see if I can answer this question for you. It may help to understand a bit of where LVPECL, PECL, etc. came from.  LVPECL, PECL are all simply variations of ECL that operate from a positive supply instead of a negative supply like ECL did. ECL (Emitter Coupled Logic) is based on emitter-coupled-pairs, or differential pairs, also known as long-tailed pairs.  Basically a differential amplifier - a pair of NPN transistors with their emitters connected together to a current source.  The base connections are the inputs.  A resistor is connected from each collector to the upper supply rail (traditionally ground for ECL).  A pair of common-collector (emitter follower) transistors are connected to the collectors of the diff-pair, and the output is taken directly from the emitters of these emitter follower transistors.

From this description, it is clear that the logic levels are referenced to the upper supply rail.  This is why ECL used a negative supply (usually -5.2V to 10K and 10KH logic, and -4.5V for the faster 100K logic) - so that the logic reference was ground (stable, good return path, etc.).  Since nearly every other logic family used a positive supply, folks started using standard ECL circuits on a positive supply, and called it PECL (for Positive ECL).  Still works, but you just have to take care about very careful layout and bypassing of the positive power supply.  Later, folks started producing families specifically designed for PECL operation (5V typ), and then later for LVPECL (3.3V typ).

In any case, the logic levels for PECL are still referenced to the positive supply.  When the diff-pair is fully switched in one direction, all of the tail current is going through one of the collector resistors, and virtually none through the other.  Typically, the maximum voltage drop across one of the collector resistors was about 0.9 to 1V.  Since the collector voltages were buffered to the output by emitter followers, the logic voltages were simply one Vbe drop below the collector voltages internally.  A logic "high" was VCC-0.8V or so, and a logic low was VCC-1 -0.7V or so.  Why would the Vbe drop be lower in the logic low case? - Because the emitter follower isn't loaded as heavy.

Since the outputs were effectively open emitters, they needed a pulldown resistor to be properly biased.  Also, since the edge speed of ECL/PECL/etc. was very fast, the lines were typically done as 50 ohm lines, thus needed 50 ohm terminations.  However, a 50 ohm resistor to the negative supply would draw *way* too much current - so the traditional termination was 50 ohms to -2V (2V below the positive supply rail).  This ensured that the emitter followers were still properly biased (sourcing current) during a logic low, and not overloaded when driving a logic high.  This was often done with a split termination - a pair of resistors that provided the Thevenin equivalent to 50 ohms to VCC-2V.

I guess the last statement would be - don't confuse the common mode voltage with the termination voltage.  Common mode voltage is the voltage midway between the logic high and low levels.  The termination voltage is the reference point that the termination resistors go to, which in the case of any ECL like output, is just slightly below the logic low level.

[uncle_bob]

Hi

So to add even more to the confusion .....

Back in the early days, two companies supplied most of the ECL parts. Motorola made theirs and Fairchild made a competing product. One would *think* that ECL would talk to ECL. Unfortunately not so much. The two families talked to each other at room temperature. As temperature of the chips changed, the Motorola parts had a very predictable change in levels. The Fairchild parts were "improved" in this respect and did not drift. The net result was that in a real system Fairchild would talk to Fairchild and Motorola would talk to Motorola. You either designed with one or with the other. Who was right and who was wrong? It's not clear that it matters after 4+ decades.

Bottom line, from it's very birth, ECL levels have been a bit of a mess.

Bob

[mairomaster]

Thanks guys! That clarified the situation.