PCB Top and Bottom pour - GND and VCC

[cheeseit]

Some great tips here!

And ditto for the dry fit, this can indeed be a time/money saver. When needed, ie. the board has to fit into something or clear something above or below the board in an enclosure, I'll print a transparency.

[elcrni]

ok, i am now well into hand routing and i like it. feel a bit lost and desperate in some moments but i think its going ok.
I have intentionally started this on as 2 layer thinking it would be a great practice. both layers GND pour but i am trying my best to use bottom layer for short tracks only, by doing so not sure this what i have looks ok. couple of things:





1. I have one main 5V connection and draw branches/traces from there, BUT at some point 've started "branching" from some of the main "branches"... is that ok?
2. trying my best to keep the cross-unders as short as possible but have a feeling i will have a lot of those by the end of this adventure.
3. i like things well organized (i am suspecting a mild OCD is well underway) and no matter how much i try to have traces as neat as possible, i have a feeling i am getting lost and will end with a mess.

Many thanks,
Alek

[phil from seattle]

For a 2L board, I generally route power first.  Try routing it around the outside of the board so you aren't "cutting" the layer in half. A power via isn't a problem unless there is a lot of current.

Also, I play with component placement a lot to try and minimize the number of crossing air wires. This is where I would sometimes use the eagle autorouter to just get a sense of how complex it is. Make all your corners 45 degrees - 2 45s is better than 1 90.

The place to try and avoid vias is in your highest speed lines. You will get a reflection.  But your design isn't that high speed in the first place.

Try to have a trace enter a pad at a right angle.  Maybe that makes me an old timer but I do try to avoid "acid traps" even though they aren't an issue any more.  If nothing else, it looks better to me.

[JohanH]

Make all your corners 45 degrees - 2 45s is better than 1 90.

Please don't say something is better without telling why. 45 degrees corners save some trace lengths of course. But if you need to make 90 degrees corners it is perfectly fine. But plainly stating that 45 is better than 90 is a myth.

[mvs]

Forget about 45° and 90°, topological routing is a next thing. 
https://en.wikipedia.org/wiki/TopoR

[jmw]

VCC should be routed point-to-point as any other signal, with point-of-use bypass, and other PDN considerations as applicable.  (A point-to-point chain topology will generally approximate a lumped-equivalent transmission line network, which is easily terminated with some resistance at one or both ends.  We don't want to draw DC current with those terminations, so an R+C is used.  Typically an electrolytic or tantalum capacitor with nominal ESR, or a ceramic with the ESR added in series as a separate resistor.)

Tim, could you elaborate here? VCC gets routed point-to-point, so between each component the trace is basically an inductance, and the bypass caps are shunt capacitance in a lumped transmission line. How would you choose the termination impedance at the end?

[JohanH]

Forget about 45° and 90°, topological routing is a next thing. 
https://en.wikipedia.org/wiki/TopoR

I guess it is time for EDAs to take next step. Computing power today is so much better, so no need to limit to 45°. Any angled corner (45°, 90° or whatever) anyway got the impedance wrong (traditionally mitigated by mitre/miter corners). But sorry for off-topic.

[exe]

As I understand, the distance between signal layer and ground plane makes a big difference. Does it me mean smaller distance is always better? Asking because at jlcpcb I can choose between 0.2mm and 0.1mm prepreg options. I suspect in some cases extra capacitance to ground can be bad. Like, current feedback amplifiers are sensitive to stray capacitances.

[elcrni]

Thanks everyone!

Next PCB preview attached. This is getting more and more out of my hands, most of the traces i am happy with but perhaps most important ones (SPI) are looking like a plate of spaghetti, i just cant avoid vias.... which further got me reading a lot more about signal integrity which the got me back to the start of this topic where it was explained that basically SPI is too slow to worry about signal integrity...
I still have to stich GND planes and sprinkle GND vias around as that seems to be the big issue with MAX7219 ICs.

so, i know i am repeating the question but would all these vias on SPI affect anything?

On the second image is my working prototype, and when i say working, i mean it runs without any glitches on any of 15 MAX7219 displays, for almost a year now. Pardon my wiring :-) what started as a prototype ended up as working piece.





Many thanks,
Alek

[T3sl4co1l]

Tim, could you elaborate here? VCC gets routed point-to-point, so between each component the trace is basically an inductance, and the bypass caps are shunt capacitance in a lumped transmission line. How would you choose the termination impedance at the end?

Sure.  The effective impedance is sqrt(L/C), where L is the average trace inductance and C is the average bypass cap.  It helps that these be similar (small variance to the average), as large excursions from the average will give weird peakiness to the frequency response -- as a result, the terminations may not be the expected values, or may not work as well as desired.

At the end of such a chain, the impedance will be high -- effectively all the inductances act in series and all the capacitances act in parallel, making a resonant tank with shunt C and series L, and this is easily terminated with a shunt R.  We wouldn't use R alone of course, as that would be quite wasteful; we use an R+C where the C is several times larger than the total C of that branch.

At a node where several such chains join up, the impedance will be low -- effectively all the inductances and their capacitances act in series.  Shunt R+C is ineffective at this point.  Series R||L can be used (sized by the same rule as above, solving for L of course) instead, or a large series L followed by shunt R + large C.  The latter is good when extra filtering is desired -- since, why waste an inductor on a stupid R||L that's only ever going to be a few ohms or whatever.

Note that large, very low ESR capacitors serve the same function as a star node: low impedance, so everything hanging off it can resonate against that anchor point.  Like having a bunch of wobbly sticks tied to a heavy mass, the mass barely moves while everything can flap in the breeze.

Tim

[T3sl4co1l]

Thanks everyone!

Next PCB preview attached. This is getting more and more out of my hands, most of the traces i am happy with but perhaps most important ones (SPI) are looking like a plate of spaghetti, i just cant avoid vias.... which further got me reading a lot more about signal integrity which the got me back to the start of this topic where it was explained that basically SPI is too slow to worry about signal integrity...
I still have to stich GND planes and sprinkle GND vias around as that seems to be the big issue with MAX7219 ICs.

so, i know i am repeating the question but would all these vias on SPI affect anything?

Again, vias are fine.  The things that jump out to me are:
- At the Arduino: this is fine, the top three traces on the bottom layer are clearly better dodging that bus of LEDs.  Well, arguably I guess.  As long as their bottom-left ends make room away from the next two or three traces on the bottom, bottom ground can pour around them.
- The 5V trace, from the, I don't have a clue what it is, there aren't designators on here, at least that are visible at this scale -- from the terminal block, there's a large enclosed area between the two traces dropping down to supply two chip resistors.  This makes an island of ground on the top side, which has to be stitched around to connect effectively.  Easier to just pull the 5V route down by the resistors, eliminating that island, and now stitching only has to be either side of that row of resistors, and connector (BRIGHTNESS CONTROL SWITCH?), no problem.
- Similar may be for the, whatever they are, the two smaller 4-digit displays bottom-center, currently unrouted -- those two traces dog-legging to the bottom-left may be better paired with the other two going up, saving you from enclosing the whole display area with another ground island.
- Also, those driver chips could stand to be rotated or flipped, probably.
- And if those dogleg traces are part of the SPI bus, then, a better route for the bus might be: Arduino, big display, bottom pair of small displays, left pair of small displays, dot matrix, top left displays and matrices, top center large matrix, top right matrix and display, center right large matrix, right matrices, etc.  Oh, or are those displays and matrices paired, maybe it's better to chain them in some logical or physical order.  Or if you have the serial chain all planned out, just route it back and forth, it's a mess that's what layout is for, resolving connections and you have a ton of space to do that with, it's fine.

It's hard to tell what's going on without being able to see net names on everything, so I'm making assumptions and keeping it somewhat general here.

Tim

[phil from seattle]

Make all your corners 45 degrees - 2 45s is better than 1 90.

Please don't say something is better without telling why. 45 degrees corners save some trace lengths of course. But if you need to make 90 degrees corners it is perfectly fine. But plainly stating that 45 is better than 90 is a myth.

shorter trace length.  At higher frequencies, less reflections.  and, they just look better. Yes, better EDAs might help but we are talking Eagle here.

As long as we are here, why don't you help the OP rather than critiquing people who are helping.

[elcrni]

Thanks everyone!

Next PCB preview attached. This is getting more and more out of my hands, most of the traces i am happy with but perhaps most important ones (SPI) are looking like a plate of spaghetti, i just cant avoid vias.... which further got me reading a lot more about signal integrity which the got me back to the start of this topic where it was explained that basically SPI is too slow to worry about signal integrity...
I still have to stich GND planes and sprinkle GND vias around as that seems to be the big issue with MAX7219 ICs.

so, i know i am repeating the question but would all these vias on SPI affect anything?

Again, vias are fine.  The things that jump out to me are:
- At the Arduino: this is fine, the top three traces on the bottom layer are clearly better dodging that bus of LEDs.  Well, arguably I guess.  As long as their bottom-left ends make room away from the next two or three traces on the bottom, bottom ground can pour around them.
- The 5V trace, from the, I don't have a clue what it is, there aren't designators on here, at least that are visible at this scale -- from the terminal block, there's a large enclosed area between the two traces dropping down to supply two chip resistors.  This makes an island of ground on the top side, which has to be stitched around to connect effectively.  Easier to just pull the 5V route down by the resistors, eliminating that island, and now stitching only has to be either side of that row of resistors, and connector (BRIGHTNESS CONTROL SWITCH?), no problem.
- Similar may be for the, whatever they are, the two smaller 4-digit displays bottom-center, currently unrouted -- those two traces dog-legging to the bottom-left may be better paired with the other two going up, saving you from enclosing the whole display area with another ground island.
- Also, those driver chips could stand to be rotated or flipped, probably.
- And if those dogleg traces are part of the SPI bus, then, a better route for the bus might be: Arduino, big display, bottom pair of small displays, left pair of small displays, dot matrix, top left displays and matrices, top center large matrix, top right matrix and display, center right large matrix, right matrices, etc.  Oh, or are those displays and matrices paired, maybe it's better to chain them in some logical or physical order.  Or if you have the serial chain all planned out, just route it back and forth, it's a mess that's what layout is for, resolving connections and you have a ton of space to do that with, it's fine.

It's hard to tell what's going on without being able to see net names on everything, so I'm making assumptions and keeping it somewhat general here.

Tim

Many thanks Tim.

You're pretty much spot on on all net names and your observations are well worth thinking about.
I have 2 chains of 8 MAX chips but as you said, numbering order is all messed up at the moment. I had it that way on my prototype and now just brought the same chain order to a PCB.
There are for sure better combinations than the order i have now, not sure if i should start over and just later change the order in the code.

a quick sketch of how tracing could be much easier and better. on 2L board, i am sure i can not avoid vias on SPI but what i have at the moment seems like a mess. Also, ICs a hard to acces with 3 traces for SPI, i can either put vias on SPI or later put many more vias on IC to display traces.



Many thanks,
Alek

[elcrni]

Oh, or are those displays and matrices paired, maybe it's better to chain them in some logical or physical order.  Or if you have the serial chain all planned out, just route it back and forth, it's a mess that's what layout is for, resolving connections and you have a ton of space to do that with, it's fine.
Tim

Yes, i had the serial chain planned out in prototype and i would pretty much like to keep it as it is, even though it may not be logical or physical order. I did route it back and forth but can not escape the feeling that i have created a mess on SPI traces and that i may have undesirable effects with the board.
I do have a lot of available space, most if not all traces have only GND below and with some further stitching, should be ok i guess.

Thanks,
Alek

[elcrni]

it seems i have forgotten to mention perhaps the most important thing about my SPI, as i am NOT using hardware SPI on arduino but random pins ("software bitbang") and "LedControl" library that does not require hardware SPI.
I have measured CLOCK speed on a designated digital pin and i got 46kHz, so this would basically make those resistors on SPI lines redundant? or i still need those? I have 2 chains, 8 MAX7219 ICs each (as that seems to be max with LedControl).
Also, fastest display change interval is 1 second.

This in return gives me the choice to shift the pins i now have for SPI to other set of pins, so i can avoid the mess with traces going from Arduino at this moment.

Thanks,
Alek

[exe]

I have measured CLOCK speed on a designated digital pin and i got 46kHz, so this would basically make those resistors on SPI lines redundant.

It's not about signal fundamental frequency, it's about raise and fall times of the signal, signal levels and peak current. A 1Hz signal is perfectly capable of creating lots of interference at each cycle. Perfect square wave has infinite number of harmonics.

[cheeseit]

This in return gives me the choice to shift the pins i now have for SPI to other set of pins, so i can avoid the mess with traces going from Arduino at this moment.

I regularly move microcontroller peripherals, inputs and outputs to other pins while laying out a board to simplify routing. One thing is doing the schematic and assigning functions to pins, another is doing the layout and I don't have the experience nor smarts to predict the optimal pins for a given function before doing the layout on a modestly complex board. Same thing with logic chips. I'd think this is common practice.

Schematic to breadboard, write code and get things working. Then I start on the board layout and modify the schematic, breadboard and code to aid placement and routing following best practices as I know them. Lather, rinse, repeat.

[elcrni]

Many thanks everyone for all the help!
Mo board is almost ready to hit production, going through the last round of checks to make sure everything is where it should be.
now thinking i would add Schmitt trigger for my encoder and perhaps switches, even though i do have RC filters on all of them, and not that i really need Schmitt as everything is working as it should without it, but thought i may include it in this design to test it and perhaps evaluate for future projects.
The thing i was wondering about is the location od Schmitt I, does it matter? Does it need to be close to Encoder/switches or MCU?

oh and another one, i have 2 MAX7219 ICs that only drive one 4 digit display, so i have unused pins, do these need to be terminated in any way or to just leave them unconnected?

Will post my finished layout later today once everything is ready.

Many thanks,
Alek