I fully understand that my PIC has a Comparator, DAC and Vref=1.024v (which is stable for Vdd 2.5V and higher). (My PIC also has internal Brown-out LO enabled, which keeps the PIC in RESET when Vdd falls below 2.35v~2.58v.) While I could indeed use an interrupt in conjunction with the Vref and Comparator, the fact is that I sometimes write to the high-endurance flash inside the PIC which takes 2.5ms-max during which time interrupts must be disabled. That 2.5ms is probably short enough not to pose a problem, but using the TLV3012 GeorgeOfTheJungle proposed along with two 1% voltage-divider resistors and a P-MOSFET (DMG2301L, which you proposed) would be a bullet-proof external solution that would be faster than using the PIC.
I think what you might be missing is that the Comparator is able to expose all of it's pins to the external world, and doesn't rely on the PIC CPU to operate. It will operate whether interrupts are enabled or not. So you effectively have a TLV3012 inside. No need for an external part to get exactly the same functionality.
At initial power on, the PIC's comparator wouldn't be configured to be connected to the FET. So the unit would stay off until ready.
Once your PIC has started, you enable the 1.024v reference, enable the comparator, and assign pins. At this point forward the comparator works just like a TLV3012. You use the same divider 1M and 820K, hooked up to the comparator input pin. The output pin is just like the TLV3012 and hooked to the FET. Once set up, it's just as fast as the TLV3012 (well, that's not true, the one in the PIC responds in 0.8uS max, vs the 12uS of the TLV3012 so the PIC is actually a lot faster).
The main advantage of this (other than the part savings) is that you can gain some software control as well. If you find you have a glitching power supply on startup, you can then delay the power on for the device. You can also force minimum off times after a drop.
I also notice that the comparator can be configured in software to add some hysteresis which will prevent 'chattering' near the threshold. I.E. once it shuts off, the voltage on the reference pin has to rise to 1.224V before the unit comes on automatically. With a normal comparator, you'll find you have glitches as the voltage crosses the threshold unless you add feedback circuitry, this avoids that hassle.
The interrupt I suggested only comes into play if you also want to turn off the TX pin to avoid currents through the TX pin powering the remote device, which is a definite possibility. Which you're already aware of:
• Use N-MOSFETs to cut Rx & Tx at the same time Power is cut to the fingerprint sensor, as per IanM. But I am still not clear on Vgs vs Vgs-thresh, so if anyone reading this could kindly steer my feeble brain in the right direction, I would appreciate it. Toward that end, here is the content of Reply#27 which never got a response from anyone...
You probably don't need to cut the sensor TX/PIC RX line. You're concerned about power from the PIC TX line being fed into an off sensor, and it powering up the device, not the other way around.
The software interrupt would probably work really well, well except when it is too slow. Other options:
1) Use a NPN transistor with the base fed from the pic TX line with an appropriate series resistor, the emitter to ground, and a pullup from the collector to the switched Vcc for the sensor. The size of the pullup resistor combined with the cable capacitance will determine the maximum baud rate (smaller=faster). You'll also need to set the pic to invert the TX line so the inversion done by the transistor is undone. I've done this numerous times and it works well depending on the baud rate. I think I'm running a 10K resistor at 19,200 with much worse cables than you have. Note that since serial idles high, generally this isn't going to consume any meaningful current until there is data on the line. You'll also want to make sure that the Vce(sat) is low enough to end up with a voltage below V
IL on the sensor (the low voltage threshold) since the transistor can't pull the line down below Vce(sat).
2) Replace the NPN transistor with a N channel fet. This would avoid the potential Vce(sat) issue, but only with a correct FET selection (see below). The Rds(on) will need to be low enough such that the voltage divider created by the pullup resistor and Rds(on) doesn't introduce the same V
IL issue.
3) Use a tri-state buffer gate. These are available around ten cents US in reasonable quantities. After some digging, I found the SN74LVC1G240 which has a active-low output enable which matches the polarity of the output of the comparator when driving a P-Channel FET. There are also active-high output enables. You'd power these from the same VCC as the PIC, and then tie the OE pin to either the output of the comparator, or the switched HV rail depending on the OE polarity. This would effectively turn off the TX pin when the power goes off. Note that the SN74LVC1G240 I mentioned has an inverting gate, so you'd need to invert the TX pin on the PIC like the above solution. Some of the others don't invert, but the ones I found don't have an active-low OE pin, and I think I'd want to tie this to the output of the comparator so that this pin shuts off as quickly as possible instead of starting after the PCH fet turns off.
4) A probably non-option: Use a fet as a 'true switch' in the dataline. I can't get my head around how this would work reliably in the signal line without a lot more circuitry. I'll explain below.
But first to help you with the FET questions:
If you look at Figure 2 in the 2n7000 datasheet at
https://www.onsemi.com/pub/Collateral/2N7000-D.PDF, you'll find a chart which shows the drain current at a certain gate voltage.
If you look at this chart, you will find that in order to reliably get 200mA through the device you'll need at least 4V of Vgs, which is the voltage between gate and source. This is more than 3.3V. If you look at 3V, you'll find that the mA is pretty close to zero... so it really isn't all that functional at 3V. Vgs(th) is the point where the fet is just starting to turn on, not the point where it is fully on.
Compare figure 2 at the DMG2310L datasheet at
https://www.diodes.com/assets/Datasheets/DMG2301L.pdf . Note at 3V you can actually push 10A through it. The Vgs(th) of this part is down around 1V, and you'll note that the Id at this level is also close to zero.
Another chart of interest in the DMG datasheet is figure 4. This is Vgs voltage vs on-resistance. You'll notice that the resistance doesn't really start dropping until somewhere just below 2V. At 3V, it's pretty close to as good as it can get, and any additional voltage isn't really all that helpful. So this Fet is really useful only above 2V with 3V or over being ideal.
In option #2 above, I said that you'd need a N channel FET. I just did a quick search, it looks like a FDV301 would probably work - in fact the Fairchild datasheet shows this very application. There are others, that's just the first one I found. I typically don't use N channel fets since I'd typically need a higher Vds, and at the voltages I use, NPNs are much more widely available and less expensive.
A quick hint: The spec which is usually listed in the part summary which will quickly tell you if you should look further is a line which will be something like:
Rds(on) = 5\$\Omega\$ @ Vgs = 2.7V.
This says the transistor will have a resistance of 5 ohms at 2.7V. If you don't see a reasonable value below the voltage of operation, look on.
One other note before I move on: There is one area where Vgs(th) is important - that is to turn *off* the device. If you have a very very very low Vgs(th) being driven by something which can't get Vgs lower than the number shown, you won't be able to turn off the device.
There are other interesting characteristics, but those are probably the biggest ones to watch for.
Now, back to option #4:
So, let's assume you put a fet in the data line as a switch. I.E. you break your dataline, and insert the fet into the dataline with G and D attached to the two sides of the 'break'. With a N channel FET, to turn the FET on you would have to raise the gate above the voltage S terminal by the voltage described above. So in your 3.3V data line, you'd need something like 7 volts on the Gate terminal to turn on the data line when the data line is high (since you start with 3.3V, then need 3V more or so).
With a P channel FET, you need to have the gate voltage below the S terminal by the appropriate voltage described above. This is why the specs in a P-channel datasheet are almost all negative. So for high voltages on your data line @ 3.3V, this is easy, you just yank the gate to zero and you get -3.3V. But now, what about low... Well, at 0V on the data line, your 0V gate voltage isn't going to be low enough to turn the FET on, which will result in a floating dataline. To fix this you'd have to have the gate voltage be below zero.
I'm sure there might be tricks to make this work with a FET inline as a switch, without a lot of level shifting of the Gate, etc., but I find options 1,2, and 3 above to be a lot more straightforward.
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