The clamp isn't symmetrical about ground because the JFET gate potential sits at a few hundred mV negative and needs headroom for the possibility of lower transconductance JFETs or running a lower Id.
The diode of that pair with both A and K tied to ground simply isn't used.
Ah ha, I thought there must have been a reason for it but I couldn't think of why, makes sense now. I learned a new thing today.
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When you first apply power don't be alarmed that the output is railed out and that the lower two LEDs aren't initially glowing. That's normal because the JFETs are saturated and grounding the emitters of the cascodes until the servo loop has stabilized the quiescent DC operating point. It takes 30 or 40 or 60 seconds or so. Sorry I don't have a BOM. Don't go changing any resistive dividers or time constants anywhere.
I figured it all out from the schematics. I'm using all 1% 1206 50ppm resistors and haven't changed any values.
I did put the capacitors you mounted point-to-point on the input, output and power jacks, directly on the PCB right next to the PCB mounted jacks I used.
Can you list what values you used, just so I can be in the ballpark?
The board layout looks like it has a few points that are not ideal: the input JFETs are quite a bit spread out and relatively close to the power transistors from the power supply section. The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.
The board looks like there is a ground plane - for good precision one should have a defined ground path for the signal. So R42 should be closely linked to ground of the input terminal. With only 1 Ohms trace resistance can also become an issue.
I don't see the input capacitor C1 - ideally this should be a low loss type like PP. NP0 caps are not yet that practical at 1 µF. So even if most of the board is SMD, I would consider space for a relatively bulk PP film type.
I'll take a look at those points and make some adjustments to the layout. I can probably scrunch up the fets etc a bit that will give me space to move them further from the power supply. Maybe I could break the ground plane between the fets and power supply too, to provide a bit of a barrier to heat conduction as well?
I wonder if a copper heat spreader on top of the fets to help equalise heat between them would make any difference?
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As for C1 (and C9), I used an SMD film capacitor, a Wima SMD-PET, 1uF 63 VDC/40 VAC part, but I might bump C1 up to a 250 VDC/160 VAC part to be on the safe side.
The datasheet for this part is linked here, let me know if you think this part is no good.
https://www.wima.de/wp-content/uploads/media/e_WIMA_SMD_PET.pdf
There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.
Would a couple of ohms do it? I won't be testing anything over 100V, my highest voltage PSU that I want to test output ripple on kicks out about 65V maximum.