Low noise amplifier.

[Kleinstein]

The board layout looks like it has a few points that are not ideal: the input JFETs are quite a bit spread out and relatively close to the power transistors from the power supply section. The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.
The board looks like there is a ground plane - for good precision one should have a defined ground path for the signal. So R42 should be closely linked to ground of the input terminal. With only 1 Ohms trace resistance can also become an issue.

I don't see the input capacitor C1 - ideally this should be a low loss type like PP. NP0 caps are not yet that practical at 1 µF. So even if most of the board is SMD, I would consider space for a relatively bulk PP film type.

There are a few points with the circuit:

I don't think one really needs the trimmer for the output balance - just 2 good resistors should be good enough.
I would more think about a trimmer or optional parallel resistors to adjust the temperature drift, possibly even with the option to go close to zero. There are a few point where one could do a TC adjustment,  e.g. via the exact JFET current. It may need coarse adjustment at the current source for the amplifier: the current source currently has quite a bit of negative TC, so the current going down with temperature. It may take a diode (or even 2) in series to R22/24/26/28 to compensate.

It is also odd to have kind of parallel current source and separate cascode transistors and still directly couple them. With more like 3 or 4 more separate current paths one could get better current sharing and better see errors (e.g. no well matched transistors). So each of the cascodes (Q5,Q10,Q15) could get it's own current source. They would be combined though 3 extra resistor (e.g. 100 Ohms range) before R35.

There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.

[GK]

The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.

The "power supply" is just a pair of so-called capacitance multipliers. The pass transistors are essentially only dropping a potential of one Vbe each. The power dissipation of these two beefy SOT-223 pass transistors isn't even 80mW combined. The majority (by design) of the heat is dissipated in the current source, which is deliberately composed of many series/parallel parts to spread the heat dissipation over a wide area.

I don't think one really needs the trimmer for the output balance - just 2 good resistors should be good enough.
I would more think about a trimmer or optional parallel resistors to adjust the temperature drift, possibly even with the option to go close to zero. There are a few point where one could do a TC adjustment,  e.g. via the exact JFET current. It may need coarse adjustment at the current source for the amplifier: the current source currently has quite a bit of negative TC, so the current going down with temperature. It may take a diode (or even 2) in series to R22/24/26/28 to compensate.

That trimpot allows me to easily trim the common-mode rejection between the LNA and the differential input of my Tek plug-in to much better than what you'd get even with 0.1% resistors. And the temperature coefficient of these resistors is an order of magnitude less of a problem. It's just a "nice" feature to have in certain situations, but most of time the output is most conveniently used single ended.

It is also odd to have kind of parallel current source and separate cascode transistors and still directly couple them. With more like 3 or 4 more separate current paths one could get better current sharing and better see errors (e.g. no well matched transistors). So each of the cascodes (Q5,Q10,Q15) could get it's own current source. They would be combined though 3 extra resistor (e.g. 100 Ohms range) before R35.

It's not odd and your suggested additional complication would be rather pointless as the current "sharing" between the individual cascodes has absolutely nothing to do with the matching between Q5, Q10 and Q15 - except only for differences in hfe, which are totally negligible.   

There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.

This part actually has some sense, but it will take a quite high voltage source to zap a MMBD-7000 through a 1uF cap. For standard DC potentials of around +/- 15V or less, there is not problem at all by a safe margin. For this reason, I did not complicate the design with additional protection circuitry. If you want to measure the output noise of a 400V DC source, then you will need to employ additional precautions.
 

[Gerhard_dk4xp]

I made an op-amp version with ADA4898 roughly based on the 'lono'

You can get the Altium files for the current, still unbuilt version. (only small cleanups
over the version with the large input Cs and their protection circuit)
Requests for improvement could be considered for abt. 4 weeks.
The JFET version has higher priority.

BTW. That's how the previous version of the lono looks like when you remove the
wet tantalum for a test and forget about it when trying to measure the noise
of a Lithium battery.  Good parts recovered, the relays are impossible to remove.

The test was why does the equiv. input noise rise above 500 KHz. It's the layout.
Input voltage was distributed to the 20 opamps with a U-shaped trace.
That was not good enough. Laying it out as a mesh held the noise flat
to 1 MHz.

Cheers, Gerhard

[TERRA Operative]

The clamp isn't symmetrical about ground because the JFET gate potential sits at a few hundred mV negative and needs headroom for the possibility of lower transconductance JFETs or running a lower Id.
The diode of that pair with both A and K tied to ground simply isn't used.

Ah ha, I thought there must have been a reason for it but I couldn't think of why, makes sense now. I learned a new thing today.

When you first apply power don't be alarmed that the output is railed out and that the lower two LEDs aren't initially glowing. That's normal because the JFETs are saturated and grounding the emitters of the cascodes until the servo loop has stabilized the quiescent DC operating point. It takes 30 or 40 or 60 seconds or so. Sorry I don't have a BOM. Don't go changing any resistive dividers or time constants anywhere.

I figured it all out from the schematics. I'm using all 1% 1206 50ppm resistors and haven't changed any values.
I did put the capacitors you mounted point-to-point on the input, output and power jacks, directly on the PCB right next to the PCB mounted jacks I used.
Can you list what values you used, just so I can be in the ballpark?

The board layout looks like it has a few points that are not ideal: the input JFETs are quite a bit spread out and relatively close to the power transistors from the power supply section. The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.
The board looks like there is a ground plane - for good precision one should have a defined ground path for the signal. So R42 should be closely linked to ground of the input terminal. With only 1 Ohms trace resistance can also become an issue.

I don't see the input capacitor C1 - ideally this should be a low loss type like PP. NP0 caps are not yet that practical at 1 µF. So even if most of the board is SMD, I would consider space for a relatively bulk PP film type.

I'll take a look at those points and make some adjustments to the layout. I can probably scrunch up the fets etc a bit that will give me space to move them further from the power supply. Maybe I could break the ground plane between the fets and power supply too, to provide a bit of a barrier to heat conduction as well?
I wonder if a copper heat spreader on top of the fets to help equalise heat between them would make any difference?

As for C1 (and C9), I used an SMD film capacitor, a Wima SMD-PET, 1uF 63 VDC/40 VAC part, but I might bump C1 up to a 250 VDC/160 VAC part to be on the safe side.
The datasheet for this part is linked here, let me know if you think this part is no good.
https://www.wima.de/wp-content/uploads/media/e_WIMA_SMD_PET.pdf

There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.

Would a couple of ohms do it? I won't be testing anything over 100V, my highest voltage PSU that I want to test output ripple on kicks out about 65V maximum.

[GK]

The clamp isn't symmetrical about ground because the JFET gate potential sits at a few hundred mV negative and needs headroom for the possibility of lower transconductance JFETs or running a lower Id.
The diode of that pair with both A and K tied to ground simply isn't used.

Ah ha, I thought there must have been a reason for it but I couldn't think of why, makes sense now. I learned a new thing today.

When you first apply power don't be alarmed that the output is railed out and that the lower two LEDs aren't initially glowing. That's normal because the JFETs are saturated and grounding the emitters of the cascodes until the servo loop has stabilized the quiescent DC operating point. It takes 30 or 40 or 60 seconds or so. Sorry I don't have a BOM. Don't go changing any resistive dividers or time constants anywhere.

I figured it all out from the schematics. I'm using all 1% 1206 50ppm resistors and haven't changed any values.
I did put the capacitors you mounted point-to-point on the input, output and power jacks, directly on the PCB right next to the PCB mounted jacks I used.
Can you list what values you used, just so I can be in the ballpark?

The board layout looks like it has a few points that are not ideal: the input JFETs are quite a bit spread out and relatively close to the power transistors from the power supply section. The power supply section is a possible source of variable heat and should thus be more separated, possibly even using THT power transistors.
The board looks like there is a ground plane - for good precision one should have a defined ground path for the signal. So R42 should be closely linked to ground of the input terminal. With only 1 Ohms trace resistance can also become an issue.

I don't see the input capacitor C1 - ideally this should be a low loss type like PP. NP0 caps are not yet that practical at 1 µF. So even if most of the board is SMD, I would consider space for a relatively bulk PP film type.

I'll take a look at those points and make some adjustments to the layout. I can probably scrunch up the fets etc a bit that will give me space to move them further from the power supply. Maybe I could break the ground plane between the fets and power supply too, to provide a bit of a barrier to heat conduction as well?
I wonder if a copper heat spreader on top of the fets to help equalise heat between them would make any difference?

As for C1 (and C9), I used an SMD film capacitor, a Wima SMD-PET, 1uF 63 VDC/40 VAC part, but I might bump C1 up to a 250 VDC/160 VAC part to be on the safe side.
The datasheet for this part is linked here, let me know if you think this part is no good.
https://www.wima.de/wp-content/uploads/media/e_WIMA_SMD_PET.pdf

There is no series element for protection at the input. Connecting to a DC source give quite some current spike, that might damage the protection and possible the DUT. This is kind of a tricky topic, as the protection can introduce noise. So the common way is to have a series resistor that can be bridged with a switch. After the DUT is connected.

Would a couple of ohms do it? I won't be testing anything over 100V, my highest voltage PSU that I want to test output ripple on kicks out about 65V maximum.

The point-to-point capacitors are just a measure of RFI protection, nothing critical. Just don't use something which will kill bandwidth or add unnecessary input capacitance.

This amplifier uses low-capacitance RF JFETs happy to oscillate at UHF and there is 12 of them in parallel for a huge net input stage transconductance and gain. Don't start tearing up/splitting your ground plane and substituting with point-point spaghetti star earthing thinking this will in any worthwhile way yield better gain accuracy or stability or whatever.

With the BFs my example of this amplifier measured 270pV rt/Hz (input referred) in an A-weighted audio bandwidth. That's equivalent to the thermal noise of about 5 ohms, so you can't put much resistance in series with the input without ruining the ultimate noise performance.
 
BTW, this kind of amplifier is a massive overkill for measuring the output ripple of any typical lab power supply.

[Kleinstein]

RF design likes a ground plane, while the 1 Ohms resistor in the FB calls for a controlled ground path. Chances are one could have both - keep the ground plane for most of the circuit. This also help with an even temperature. Just get R42 close to the input ground, so there is no other current path interfering.

With the SK3557 the input capacitance will be larger. So the tendency for oscillation (and maximum speed) will be likely lower.

Thermal coupling between the FETs is not that critical. It is more the par with the LEDs and transistors for the current sources that should be coupled to the FETs. Thus the idea to have 4 transistors so they can be on different sides. I am still not sure about the overall temperature effect. The current sources will show a significant negative TC. So to get a low overall TC the FETs would need to operate at a relatively high current so that there higher temperature would also cause higher current. So Chances are diode(s) to compensate the TC of the current source could be a good idea.

Splitting the current sources would in deed not help with current sharing, it would only make errors visible. Probably just the resistance of the inductors at the input could be enough to see an imbalance.

[Sylvi]

Hi

I have not read the entire post so maybe my question has been answered:

What is the intended application for this circuit?

[TERRA Operative]

One application is increasing the amplitude of small signals by a known amount to make measurement and display easier, then you divide your results by the known gain of the amp and you have your actual signal.

BTW, this kind of amplifier is a massive overkill for measuring the output ripple of any typical lab power supply.

Yeah, it's just one of the uses I'll put it to. But when it comes to test & measurement, overkill is always more fun.

[TERRA Operative]

Alrighty, I've had a bit of a bump around with the layout.
I scrunched the FET's up a bit and moved them further away from the power supply section, moved R43 right near the input jack and fattened up the traces too, uprated C1 to a 250VDC film cap, and tweaked a few other bits and pieces around the place too.

Hopefully that looks good enough to use now?

[awallin]

What is the intended application for this circuit?

if you want to verify the performance [1] of a low-noise part like a good voltage-regulator [2] - then the voltage regulator spec of 2 nV/sqrt(Hz) is just around twice the noise of a 50-ohm termination resistor - so you need an amp like this in front of your spectrum-analyzer/scope/DMM.

the applications are limited by the need for a low source impedance. any sensor or source with a large output impedance will be much noisier than the LNA..

[1] https://www.analog.com/media/en/technical-documentation/application-notes/an83f.pdf
[2] https://www.analog.com/media/en/technical-documentation/data-sheets/3042fb.pdf

[Kleinstein]

The ground plane on the bottom side look horribly fragmented. This is no longer a working ground plane.

The supply is supposed to be at some +-15 V with already good regulation (except for the filter caps the PSRR is not expected to be very good).
With a +-24 V supply chances are the heat production could be a little high in some cases. I would more prefer a lower supply - not sure how low it can be, but it may work with some +-12 V and maybe with +12 V and only -5 V.

For the input capacitor, the question is not if 40 V or 200 V polyester. The question is more if a polyester cap is good enough: due to the DA the initial settling can take quite a while. With a PP cap the settling could be faster.

[TERRA Operative]

The original design didn't have a ground plane on the back at all, is it better to have none rather than one that is a bit cut up? I have vias everywhere stitching the top to bottom ground planes so there aren't any 'tails' that might act as an antenna as such (pending any I missed). Maybe a 4 Layer board would give better results?

Good catch on the 24V, that's a typo on my part. I was playing with some 24V SMPS modules for another project and had that number on the brain. It's been corrected to 15V now.

For the 1uF capacitor, would the couple tenths of a percent difference make much difference? I assumed it would have been small enough to not be too bad (I'm certainly no expert though...)
How about a PPS capacitor like this? PPS seems to have a similar dielectric absorption to polypropylene.
https://www.wima.de/wp-content/uploads/media/e_WIMA_SMD_PPS.pdf

[Sylvi]

Hi

I actually wanted to hear from GK since he is the one that started this thread and presumably he is the one with the need for this amplifier?

I know any basic building block with gain can be used for a wide variety of purposes.

What is GK's purpose for it?

[Kleinstein]

I don't think one would need a 4 layer board. Some vias to connect / patch the ground plane should be enough. One may a reduce the fragmentation if needed.

The expected effect of a MKS type or similar capacitor is that after a larger voltage jump, one would see some low  DC / very low frequency drift over quite some time of maybe 1-10 minutes - more than the normal RC time constant. This may be acceptable, as warm up would take longer anyway. Fast moving a probe around can be tricky anyway due to the large capacitance.

For the PPS capacitor the loss factor looks good. However I remember somewhat conflicting results on DA in PPS. DA is not is not fully characterized by a single number, but is also frequency dependent. AFAIK PPS is good at some frequencies and not so good at others.
In theory also some NP0 caps can have very low loss. However I don't know the large ones and 1 µF would need something like 10 x 100 nF in parallel. Also not all NP0 are equal.

It could still be worth to have the option to use PPS if MKS is giving to much DA effect after a jump.

It really depends on the usage, but other similar amplifiers often include some series resistor at the input to limit the current when charging the capacitor.  So something like 5 K in parallel with a switch to turn of the extra protection. A 1 µF capacitor could be too much for some circuits to measure (the typical LTZ1000 reference circuit would no like connecting this amplifier).

As the shown amplifier is relatively fast, it may be suitable to use with a scope. The LF performance depends on the FETs. The use for LF noise (e.g. voltage references) may be limited, not really bad, but still with some 1/f noise.

[TERRA Operative]

I don't think one would need a 4 layer board. Some vias to connect / patch the ground plane should be enough. One may a reduce the fragmentation if needed.

The expected effect of a MKS type or similar capacitor is that after a larger voltage jump, one would see some low  DC / very low frequency drift over quite some time of maybe 1-10 minutes - more than the normal RC time constant. This may be acceptable, as warm up would take longer anyway. Fast moving a probe around can be tricky anyway due to the large capacitance.

For the PPS capacitor the loss factor looks good. However I remember somewhat conflicting results on DA in PPS. DA is not is not fully characterized by a single number, but is also frequency dependent. AFAIK PPS is good at some frequencies and not so good at others.
In theory also some NP0 caps can have very low loss. However I don't know the large ones and 1 µF would need something like 10 x 100 nF in parallel. Also not all NP0 are equal.

It could still be worth to have the option to use PPS if MKS is giving to much DA effect after a jump.

It really depends on the usage, but other similar amplifiers often include some series resistor at the input to limit the current when charging the capacitor.  So something like 5 K in parallel with a switch to turn of the extra protection. A 1 µF capacitor could be too much for some circuits to measure (the typical LTZ1000 reference circuit would no like connecting this amplifier).

Cool, I have a bunch of vias around, I'll be a little more liberal with them, and have a go at tweaking the layout to try to minimise the fragmentation.

I was just thinking designing in to have options would be the way to go with the capacitor too. A dual footprint so I can mix and match and see what works best for my use case.

I'll add the resistor and switch too. At the very least I can just not solder them in if I don't end up needing them, but at least the option is there if it is needed. Better to have it and not need it than the other way around.

[ckocagil]

Thanks. OK, it's getting on to 1am here, but who needs sleep when it's holidays. Attached is the revised schematic and I am almost done modifying the PCB layout.

Thanks for the design!

I'll build one of these. I have some questions though.

1. What's the actual input capacitance? Is it 10 pF x number of JFETs or does cascode kill it? Any ideas on simulating the effective input capacitance in LTspice?

2. What's the servo servoing here? Is it just pinning the output DC to 0 to eliminate drifts, with no regard to input DC?

[Kleinstein]

The cascode is not totally eliminating, but limiting the gain to Crss  (gate to drain).  So the expected capacitance per input FET should be a little more (maybe 5%) than Crss + a small part (.e.g. 5% of Ciss + some parasitic capacitance. So I would expect more like some 3-4 pF per FET.

The servo part makes sure that the output signal is DC wise close to zero. So it compensated the DC offset of the JFET stage. The input is AC couples anyway, so input DC is not an issue.