Low noise 0.01Hz-1+MHz amplifier project

[magic]

The current mirror resistors are definitely a source, and must be kept low in value, but would not be required if matched transistors were used.

Degeneration is required for suppression of the effects of voltage noise of mirror transistors. Everybody degenerates current mirrors . IC designers do it all the time. Mainstream audio design books talk about it.

The 330Ω chosen in the design here is actually about the right value, slightly more effective than 100Ω and decidedly better than 33Ω or less. Even 1Ω makes a significant difference, but 1mΩ finally doesn't seem to matter. I seem to recall that the figure of merit is voltage across the resistor (fairly high at 6mA bias) divided by thermal voltage.

Note that this is broadband noise only. Real transistors also contribute hell knows how much 1/f, but Toshiba's lousy models don't show it.

[Kleinstein]

The current mirror degeneration resistors contribute some noise, but less noise with larger resistance as it is about the noise current. Larger resistors however need more voltage headroom (higher supply) and with really high voltage drop the excess noise of the resistors can be an issue with some types of resistor. So it can be worth using at least thin film types, ideally a low noise one.

[CurtisSeizert]

The calculations sounds OK, though maybe the extrapolation to 0.01 Hz being a bit tricky with the JFETs.
The choice of the BJTs does not look that good. The HN4A51 and HN4C51 are not really made for that much current. Noise wise they are best used with more like 0.1 to 0.5 mA, especially for low frequencies.

These may not be the best parts, but among dual bipolar transistors they are almost uniquely easy to lay out for current mirrors and cascodes in diff amps. All the SOT363 duals are a PITA. The SSM2212 is not too bad, but it costs about 20x more, is bigger, and doesn't seem like it would improve things much. It would also only be applicable to the cascode stage. ADIs matched transistors are nice but also ridiculously expensive.

I am convinced the excess flicker noise in this relative to simulations is a consequence of me using JFETs harvested from earlier prototypes. I will plug in the board from the previous revision today and run a capture so I can share the FFT from that, which is somewhat better than the simulated noise. I shorted the AC coupling capacitor in that as well, so the noise of the 100M resistor does not come into play. By the way, that HP filter is responsible for about 9 nV/rtHz at 0.01 Hz, and the -3dB point in the captures I showed is also 0.01 Hz. As such, the diff pair contribution is also about 9 nV/rtHz. This sets a limit to the effectiveness of optimization of the diff pair without setting f_c of the input HP filter lower, but with a gain of 501 and supply voltages as they are, this limits the input voltage that won't rail the first stage due to the finite parallel resistance of the caps.

I am sympathetic to Magic's point of view that a simpler input stage would be better. Also, reducing the gain of the input stage diff pair to the minimum necessary to ensure the op amp's noise is not a major contributor to system noise would definitely make compensation easier and allow operating the input stage at somewhat lower gain. I also agree with David that a fully differential input stage would be better for practical probing situations, not just those where the inputs are shorted by a relay on the board itself. I will try to get the Github repo up today and link it and include the FFT of the other amplifier tomorrow.

[CurtisSeizert]

Does the first cascode, or current mirror, contribute significant noise anyway?

You would have to ask Toshiba if it's significant, I don't have the numbers for these transistors.

Actually, Toshiba gives certain numbers.

At 10Hz, HN4A51J datasheet shows 12dB noise figure at 6mA for circa 1800Ω source impedance.
Johnson is 5.4nV/rtHz and 12dB more is 21.6nV.
Subtracting Johnson, 21nV/rtHz is left. Voltage noise of the transistor is negligible, sub-1nV.
Dividing 21nV by 1800Ω (ignoring base spreading resistance) gives ~11pA/rtHz.

Repeating the calculation for 1kHz yields 2.2pA/rtHz, and this is consistent with expected shot noise of 15μA base current.
So 10Hz is well below the 1/f corner, and 0.01Hz is likely to be almost 32x more: 0.35nA/rtHz.

For the NPN we get 3000Ω, 9pA/rtHz at 10Hz and estimated 0.3nA/rtHz at 0.01Hz.
Total noise from both pairs is 0.65nA/rtHz. Dividing by 80mS transconductance of the diff pair gives 8.1nV/rtHz equivalent input noise voltage.

This is more than contribution of the JFETs at 0.01Hz (per the datasheet and SPICE model).
It's a pessimistic estimate, assuming exactly 1/f distribution below 10Hz. Perhaps real world is slightly better, but maybe not much better.


Or did I screw up the calculations?
I believe I originally got this procedure from The Art of Electronics, and it sounds sensible. I mean, the part about converting NF plots to i_n and e_n; the extrapolation to 0.01Hz is a separate matter.

I believe the current noises are uncorrelated. I modeled the current noise of one of the cascode transistors as a current source in LTSpice. With an amplitude of 0.3nA for AC analysis, V(out)/501 * sqrt(2) gave 5.8nV, which would of course equate to 5.8 nV/rtHz RTI. That indeed would be significant and would be comparable to the JFETs at that frequency.  That current noise, incidentally, is converted to voltage noise with an effective transimpedance gain of 1733 Ohms at the base of the cascode transistors, which I have brought out of the shield with a test point. The voltage gain of noise at the noninverting input at that node is approximately unity. I may try to see how much this matters by probing that point, but I will need to build a second LNA to do so effectively.

With regards to sources of excess noise over the simulation, when I initially assembled the board, I did not wrap foil tape around the capacitors, and the drain of an MMBF4117 was connected to the input node, with its gate reversed biased to the negative rail (-4V3). Under these conditions, the noise at 0.01 Hz was in the neighborhood of 20-25 nV/rtHz, My recollection is that removing the 4117s and putting copper foil on the input and first HP filter capacitor had approximately equal impacts on LF noise [Edit: looking over previous data, most of this was from the MMBF4117s, and the foil was for stability - the cap after the first stage appeared to radiate to the 2x12uF AC coupling caps, causing positive feedback]. Moreover, the input JFETs are absolutely not biased close to their zero tempco point, which would require a tail current of about 14 mA * 16 JFET pairs. I haven't done a temperature sweep to see what the input Vos temp co is, but for a first pass calculation, let's say the datasheet figure holds for the drain currents in this design and that the tempcos are symmetrically distributed around zero. This would mean the Vos temco is around 425 nV/K, though it is likely worse, because both of those assumptions are likely false and would tend to underestimate it. The 0.01-1 Hz RMS noise (i.e., that more in frequency ranges where thermal fluctuations happen) is 2.2 nVRMS. As such, temperature fluctuations around 5mK (RMS) over 0.01-1 Hz would likely be sufficient to explain all the noise, assuming the estimated Vos TC is close, not just that which is in excess of the simulation. This is not too difficult to achieve, but such thermal variations only need to account for part of the measured noise, and the TC is probably worse than my back-of-the-envelope calculation. There are also, of course, parasitic thermocouples, which are a bit difficult to quantify but are still undoubtedly important. I have generally taken long captures in a steel box. This isn't critical for short measurements, but it helps avoid things that lead to "noise" such as touching the case while wearing socks, wearing socks in the vicinity of the amplifier, opening the door too quickly, etc. I believe this sensitivity is mostly a consequence of the big PP caps acting as antennas.

I have attached a preliminary VSD plot from the previous version of the amplifier. In this case, the 1/f corner is around 1 Hz. The non-inverting input of the first stage is shorted to ground here rather than through capacitors to isolate the effect of the input amplifier. The input stages are the same for the two versions, with two minor exceptions that I know to be inconsequential. The load resistors are 33k in this rather than 10k, and there is no resistor at the source of the PMOS that biases the folded cascode. Layout of the input stages is identical other than the routing of the traces for the input gates of the first stage. The main change was incorporation of the PP capacitors. Previously, I used paralleled 470nF C0G capacitors in place of all of these. In retrospect, the choice of the C0Gs for the HP filters other than the AC coupling one was probably a good choice. The bottom of the input stage is also shielded in this design. Both use BMI-S-230 shields, which have a solid cap rather than a perforated one. With the large AC coupling caps, I no longer had sufficient clearance for the bottom shield without redesigning the BMS board, so I had to remove it, and I had to switch to somewhat smaller shields that only have perforated covers. Also, as I have previously mentioned, the JFETs in this one were new and the ones in the current version had been salvaged. In any event I have not figured out the reason why this is so much better than the current version, but it is also notably better than the simulation. In all likelihood, the BJTs used in this design were adjacent on the reel to those used in the previous one. I'll get a longer capture of the noise floor for this design and add it to this response tomorrow.

Edit: As mentioned in a later post, I not longer believe the NSD shown in this post to be valid, so please disregard it.

[moffy]

I have thought that some RF transistor pairs would make good low noise transistors for the audio range because they need a low Rb to be effective at RF e.g. https://au.mouser.com/datasheet/2/302/BFU520Y-3138076.pdf
Can anyone elucidate as to whether that assumption is correct or false?

[magic]

I haven't done a temperature sweep to see what the input Vos temp co is, but for a first pass calculation, let's say the datasheet figure holds for the drain currents in this design and that the tempcos are symmetrically distributed around zero. This would mean the Vos temco is around 425 nV/K, though it is likely worse, because both of those assumptions are likely false and would tend to underestimate it. The 0.01-1 Hz RMS noise (i.e., that more in frequency ranges where thermal fluctuations happen) is 2.2 nVRMS. As such, temperature fluctuations around 5mK (RMS) over 0.01-1 Hz would likely be sufficient to explain all the noise, assuming the estimated Vos TC is close, not just that which is in excess of the simulation.

That's quite sensitive.

Regarding offset and drift distribution, in theory they should be symmetric around zero if the internal layout of the chip is symmetric. But the datasheet shows shifted distribution of offset voltage, so it's right to be suspicious about drift as well. What can break such regular asymmetry is installing half of the chips rotated 180° to swap the sides, which you seem to have done already. It could be better to use checkerboard pattern, or any other where the "center of mass" of each group is exactly in the same point.

Another potential source of offset and drift is base current of the mirror, but I haven't tried calculating if its influence is worth worrying about.

I have attached a preliminary VSD plot from the previous version of the amplifier. In this case, the 1/f corner is around 1 Hz.

This looks very good and given what we believe about significance of the BJTs, it seems to imply their current noise may be better than worst case estimates.

[moffy]

I don't know how how accurate the BFU520D model is or how well my circuit is for testing but here is the result.

[Roehrenonkel]

Hi moffy,

I have thought that some RF transistor pairs would make good low noise transistors for the audio range because they need a low Rb to be effective at RF e.g. https://au.mouser.com/datasheet/2/302/BFU520Y-3138076.pdf
Can anyone elucidate as to whether that assumption is correct or false?

Yes that's true. I've seen a lot of MC-PrePreamps (Phono) with HF-transistors.
Rb (internal) is contributing much to the noise.

Best regards

[CurtisSeizert]

Regarding offset and drift distribution, in theory they should be symmetric around zero if the internal layout of the chip is symmetric. But the datasheet shows shifted distribution of offset voltage, so it's right to be suspicious about drift as well. What can break such regular asymmetry is installing half of the chips rotated 180° to swap the sides, which you seem to have done already. It could be better to use checkerboard pattern, or any other where the "center of mass" of each group is exactly in the same point.

Another potential source of offset and drift is base current of the mirror, but I haven't tried calculating if its influence is worth worrying about.

I have found that TI sometimes turns Vos TC values into absolute values in their datasheets, and I believe their usual practice for typical values is to report typical as one standard deviation from the mean. They explain this in the OPAx205, and other, datasheets. Unfortunately, this leaves one to wonder what the typical value actually refers to in some cases. For the delta_VGS they have a histogram that does show it not to be centered around zero. For the pinout at least, the clamping diodes break rotational symmetry. I considered doing a checkerboard pattern, but in the end I was too lazy. Some of the FETs are turned in such a way as to minimize the trace length to the gates of the inverting input and keep parasitic capacitance to a minimum for stability. The first stage output centers around 280 mV with no signal, so the Vos of the amplifier as about 560 uV. This is remarkably close to the simulated value (about 250 mV), so a large part of the offset may be base current from the mirror transistors. Changing the emitter degeneration resistor to 332 for the diode-connected transistor would get pretty close to compensating this without recourse to additional bodgery. At a drain current of 400 uA, the mean delta_VGS is probably closer to zero, based both on the datasheet graph of delta_VGS vs drain current and my own testing of 42 of these at a drain current of 500 uA. At this lower drain current, the mean delta VGS was 139 uV, so I expect most of the offset is due to mirror base current. Regarding the TC, I can say anecdotally it is better at higher drain currents (as assessed by warm up drift), but I don't remember if this was symmetrical, and I did not record the values before they settled.

As promised, here is a better FFT comparing the noise floor spectra for the two revisions. I mentioned the relevant changes in my previous post. I added some more data I had gathered. The orange and green spectra were taken from captures on my 34465A using the front panel digitize function. They were also taken with 30k loads on the folded cascode. I wouldn't put a lot of stock in the low frequency part of the green trace at the moment; it isn't consistent a lot of the behavior I have seen, and I would need to repeat it with a longer capture to confirm an effect. These spectra contradict some of the earlier things I said about shielding and the influence of the input HP filter, which I must have remembered incorrectly. I will edit my previous posts to fix this. I spent a good deal of time trying to track down the source of the excess LF noise in this revision, but some of that effort was not very well organized. I have made the general observation that the previous amplifier is less prone to oscillation, and it is definitely less sensitive to environmental stimuli, like touching the case. The spectrum in my previous post was just the amplifier sitting out on the bench. No additional shielding necessary. I put it in a box for the longer capture because it takes a long time to run.

Edit: I don't believe the NSD trace for the "Previous Revision" amplifier noise floor to be correct due to sporadic behavior when trying to confirm the gain. Any conclusions from those data in this post should be considered suspect as well.

[NWerner]

Could you explain/speculate how it is possible to obtain much lower "frequency knee" as compared to the datasheet where the knee occurs at the vicinity of 10Hz?  It always was my understanding that (broadband) noise is very well characterized by datasheet values. But maybe the situation for 1/f noise is different?!

Are these graphs limited by test equipment or there some aspect of the design I am completely missing?

Thanks a lot for making this really cool project public

Noman

[Kleinstein]

The actual LF noise powerformance can vary quite a bit between parts, while the white noise part is usually much more consistent. There can also be small process changes that may improve things - they would counteract if it gets worse, but hardly if the get better. So there is a chance later part can get slightly better.

Another point with the LF noise is that thermal effects can be a part of it also in the tests for the data sheets. A good thermal design (sometimes also by pure luck) and symetry in using multiple parts in parallel can help. When it comes to thermal effects a symmetric layout can make 4 FETs combined much less sensitive to thermal effects.

[Gerhard_dk4xp]

If you hide the 1/f noise under enough white broadband noise,
you can push the 1/f corner arbitrarily low. All in all, that is no
reason for joy. The corner frequency as such is no real value,
it depends on the absolute amplitudes, too.

[CurtisSeizert]

I apologize - the measurements I took for the "Previous revision" amplifier (the one with the very low 1/f knee) are suspect, and I don't believe them to be correct. I will make the appropriate annotations to the prior posts where I mentioned that.

[CurtisSeizert]

I built a second one of these amplifiers, this time using a 2k49/4R99 divider (rather than 1k/2R) for the input stage. This was indeed beneficial for stability. The noise floor from this second amplifier was a bit higher as a result (640 pV/rtHz rather than 600), but the LF noise was indistinguishable. I also changed one of the load resistors from 330R to 332R and rotated half of the JFE2140s in a checkerboard pattern to account for the non-zero average Vos and VosTC (Credit to Magic for this suggestion). I have tested this second amplifier extensively and I'm pretty confident in its performance, especially since it is so close to that of the first one. There is one thing to note that I realized during this testing. The -3dB point for the 0.01 Hz HP filter is actually about 12.2 mHz rather than 10 mHz. This is because I had originally designed the filters with 4.7 uF capacitors, where a 4.7uF/10Meg HP filter would be comfortably below 10 mHz, so it would not be a big issue. I did not update this resistor when I changed to 2.2 uF capacitors. The usual measurements with LF use a first order high pass, so I will move the Fc of the first high pass filter down far enough that it remains first order in the region of interest (>10 mHz). By the way, the 0.01-10 Hz filter envelope I attached looks like there is some passband ripple, but I wouldn't put too much stock in this. With a 2 mHz starting frequency for that sweep, it was necessary to reduce the averaging, etc. to a minimum to keep the sweep inside of a day. With the 0.1 - 10 Hz Bode plot, I used more averaging and there was no passband ripple. The measured THD varied inversely with gain for the 0.01-10 Hz plot, so I am guessing there was some interfering signal that couldn't be rejected well with the measurement parameters for such a LF sweep.

Also, I dug into the current noise line of reasoning, and I am a bit confused. If someone can point out errors in my reasoning, that would be helpful. Here's how I am thinking about this: I believe the cascode situation is analogous to the AoE3 chapter 8 section about current noise in the BJT current source, which also uses a common base configuration. The gos of the paralleled JFETs is large compared to r_e of the npn, so there should be no emitter current noise (at the limit of high beta). There should be current noise at the base, of course, which would appear as voltage noise at low frequency due to the dynamic impedance of the 3 series diodes used to set the bias of the cascode. With the 28k7 resistor to Vcc in the schematics, the current running through those puts the dynamic impedance around 1.7k, but this voltage noise would be applied to the bases of both transistors, and would be rejected as common mode noise. To see if the this current noise was actually causing problems, I swapped the 28k7 resistor for a 7k68 resistor, bringing the dynamic impedance down to 350 Ohms (simulation). This had no impact on the noise of the amplifier. Also, shouldn't the shot noise be proportional to Ic/sqrt(beta) rather than Ib?

If the Toshiba model is not reflecting the 1/f character of the voltage noise of the transistor, which they definitely are not - it is a flat NSD with their model, the 1/f corner would still need to be >1 kHz for this to impact the amplifier, assuming their model for the broadband noise density is accurate.

Ultimately, I think the divergence of the LF noise from what was predicted in the simulation is more likely a consequence of inaccuracies of the SPICE model TI put out for the JFE2140. This wouldn't even be the only error in their model - they have VTOTC as 0.45m, which is definitely not accurate. Their values of VTOTC and BETATCE do not make it possible to achieve zero tempco biasing in simulation, though my measurements of actual parts puts the zero tempco Vgs around 320 mV, which is around the 0.6V higher than VgsOff that one would expect for JFETs in general.

Edit: Added the Bode plots I mentioned.

[Kleinstein]

For the shot noise Ic/sqrt(beta) and Ib should be the same - this is how beta is defined. Usually the difference between the large signal and small signal numbers is not that relevant.

The gos / re argument applies to the votlage noise and current noise * base resistor. However the current noise at the base also means there is a corresponding current at the emitter or collector.  So the current noise would still matter relative to gm.

It is a bit unusual that the current noise is supposed to get so bad with the toshiba part at higher current. This may be a thermal effect, that could be different with a lower CE votlage or layout.
The models for 1/f noise are often not very accurate.

[magic]

I believe current noise can be modeled as a random AC current between base and emitter.

The base side is not a big issue - it flows into the base bias circuit which isn't very high impedance (I presume), it's common mode if both cascode transistors share the bias circuit, and it only results in drain voltage variation which modulates drain current by the relatively low drain output admittance.

The emitter side is an issue - it simply flows into the drain, it's not correlated between the two sides, feedback loop counters it by a differential input voltage variation equaling noise current divided by differential pair transconductance. Same for noise current from mirror transistors, opamps and anything else connected with the drains.

[CurtisSeizert]

I believe I understand now. The section in AoE I was reading (Ch. 8.3 I think) is worded in an (uncharacteristically) obtuse manner, but ultimately by KCL that base current's gotta go somewhere (as Kleinstein pointed out), which I lost sight of as I got lost in the weeds. From a quick simulation, the RTI contribution of the base current noise to the noise of the stage as a whole is about i_n * 19.2 Ohms (from modeling one transistor and multiplying the result by sqrt(2)). It may actually be as bad as the worst case analysis of 0.35 nA/rtHz - the ~9.5 nV/rtHz in the spectra is actually around 15 nV/rtHz if you consider the filter envelope. Getting rid of that noise source would bring it down to 13.2 nV/rtHz at 10 mHz. I feel like the best way to deal with this is to just rig up a test jig and run the experiment. I'll probably do a simple long tailed pair approach due to the low frequency requirement and because I can adapt something I've already built. If it's bad, I could pop another JFE2140 in (with appropriate biasing modifications) instead of the NPN pair in a revision.

[Kleinstein]

There is not need to use JFETs for the cascode. There are considerably better NPN transistors when it comes the the current noise. The HN4C51 is just not made for so much current. Alone using less current per transistor may improve things quite a bit.
If this is not enough darlington transistors would be an option too, with naturally less base current.

[magic]

I think you could measure exact current noise of an individual BJT in a fairly simple test jig: ground the collector, ground the base through 1kΩ, pull 6mA from the emitter. Measure emitter voltage noise with your AC coupled LNA.

Since we expect tens to hundreds pA/rtHz, the resistor will make it same number nV/rtHz, comfortably above its own Johnson noise, transistor's voltage noise and the noise floor of the LNA.

[CurtisSeizert]

I think you could measure exact current noise of an individual BJT in a fairly simple test jig: ground the collector, ground the base through 1kΩ, pull 6mA from the emitter. Measure emitter voltage noise with your AC coupled LNA.

Since we expect tens to hundreds pA/rtHz, the resistor will make it same number nV/rtHz, comfortably above its own Johnson noise, transistor's voltage noise and the noise floor of the LNA.

Good point. I might as well put the LNA to work. I rigged it up, and I'll take some spectra tomorrow.

[CurtisSeizert]

So I built up the test jig using one half of an HN4C51J (E2 and C2 open). The collector was connected to the positive terminal of a 9V battery, and the emitter was connected to the negative terminal through a 1k395 resistor. The base was tied to the collector via a 6k745 resistor, and V_noise was taken between the emitter and collector. In operation, Ie was 5.967 mA, Ib was 22 uA (beta = 266). To get the voltage noise at 10 mHz, I extrapolated back using (averaged) numbers at 0.1 and 1 Hz (255 and 85.2 nV/rt Hz, respectively). The amplitude goes as 1/(f^0.48) over this range. This gives 765 nV/rtHz at 10 mHz, which equates to 113 pA/rtHz or a NF of 37.2 dB. I assumed here that the voltage noise of the transistor itself was negligible here, which is probably reasonable given that Rs >> r_bb + r_e.

Applying this to the LNA input stage, using the quick calculation of i_n * 19.2 Ohms, 113 pA/rtHz would give 2.1 nV/rtHz RTI, or a 1% contribution to amplifier noise for both cascode transistors. As to the source of the discrepancy with Magic's calculations, with this configuration the 10 Hz NF is 8.6 dB with ~6.8k, vs. maybe 15 dB in the datasheet (Toshiba uses a common emitter amplifier with Vce 6V).

[magic]

Interesting result and a nice transistor.

1/f corner is a decade lower than specified by Toshiba. 12pA/rtHz at 1Hz is only 10dB above OP37/LT1037, despite 50x higher collector current. It seems that good discretes can have a meaningful advantage over IC opamps in this area.


So it's still unclear where the unexpected noise comes from? I suppose you don't know what setup TI used to produce the datasheet figures?


edit
What software are you using to produce these plots? I'm trying to do some noise measurements and already wrote an Octave/Matlab script for it, but I'm not 100% confident in my DSP skills so it would help me to compare against known-good solutions.

[David Hess]

12pA/rtHz at 1Hz is only 10dB above OP37/LT1037, despite 50x higher collector current. It seems that good discretes can have a meaningful advantage over IC opamps in this area.

Precision parts like the OP07/LT1001 and OP37/LT1037 implement input bias current compensation so they have much higher input current noise than their input bias current would indicate.  For a fair comparison, use a precision part that lacks input bias current cancellation like the LT1006, or make the comparison with an integrated monolithic part like the LM395 or MAT series transistors.

I never really looked into it, but maybe the added noise from the input bias current cancellation is less than the added noise of using a balancing resistor on the non-inverting input.  Operational amplifiers that have input bias current cancellation do *not* benefit from balanced source resistance to reduce offset, although having a balanced impedance at the inputs reduces noise *if* the input bias current noises are correlated which is the case with some parts.  The LT1028/LT1128 are like this so I suspect the LT1027/LT1037 and entire LT line are also.

[eleguy]

This is clearly not a "budget" project but good work overall! I did not fully yet check the (github) schematics but at least PSU section could need some attention from the protection point of view that you have nicely started. MBR0540 V_RRM(min) is rated 40V but the caps are 35V and at least LT30402 absolutely max is only 22V. MBR0520 - which could be safer call - has same footprint (if I remember correctly). Well, one could play certainly even safer with some other brand Schottky.

[Kleinstein]

The input current noise specs for some OP-amps is also strange. E.g. for the OP27 and quite a few other they assume anti correlated noise. The correlated part is not included and uncorrelated is underestimated in the measurement they descirbe for the specs. So the actual noise specs can be worst.

There are more sources to the current noise in an OP-amp than just the input transistors. The current source to drive the long tailed part is such a source that produces correlated current noise. The comparison of an OP-amp to just 1 transistor is not really fair.
The other point is the different current level - in the LNA the transistor operates at a high current, well outside the sweet spot for the transistor.