Looking up the SOA- not so simple, assuming a reactive load will never be seen, needs a derating as running parts near these limits is a bad idea and their datasheets are full of hype.
Reactive is no problem. Fit SOA to worst case, i.e., short circuit condition. Capacitor can't draw more than that for a short time (seconds, for a fucking huge capacitor), inductor can only draw that after some time.
Oh and, inductor can only draw current the same direction as was applied. So, charging up a big fat 100H inductor then disconnecting it and watching that sexy arc draw off the terminals, makes absolutely no difference to the supply at all. Current is dropping during that arc, and voltage remains fixed at the setpoint. No flyback pulse, no crazy spikes, just a clean burn.
Derating: goes without saying. My earlier hint seems to have gone unnoticed: to use TO-247s at under 100W, and TO-220s under 50W. Typically, these will be rated upwards of 300W and 100W, respectively (depends on die size, some are less, too). The derating serves two purposes: being conservative about the actual SOA, and approximate overhead for RthJC, insulator and heatsink.
Well, derating helps reduce the impact of thermal cycling, which is also nice.
TI claims:
"As a final guarantee of the reliability of our SOA curve, we de-rate each measured thermal runaway line anywhere from 30-40%, depending on how much part to part variation we see. So when you are comparing our FETs’ datasheets to competitors’, be wary of the fact that they may not be as conservative. We have seen some vendors who are. We have seen others who publish the actual failure points and claim this as their guaranteed SOA. There is no industry standard and the truth is without the underlying data demonstrating where parts actually failed, it is impossible to know which part is more reliable from the datasheet SOA curves alone."
I tested a smaller QFET to destruction (FQPF6N40C) and it failed very close to the RthJC limit.
I haven't tested any TI transistors to destruction, so can't speak to the validity of their claims.
Anyway, all this talk about SOA works the other way, too: you can buy a handful of different transistors, and test each one. Once the supply is complete, and tested for operating characteristics, test it under short-circuit load (protip: don't actually short it, use a low ohm fusible resistor instead). Test different brands and increase the current limit gradually until destruction occurs. This plots a single point on the SOA curve.
If that point lies inside the DC SOA curve, that manufacturer is full of shit.
If outside, they're being conservative.
Like I said before, Si IRF740 is not specified for DC, but I have tested it for DC and it passed with a whopping 60% or so of headroom.
There's no secret to it. You hook it up and either it works or it doesn't! This is literally all the manufacturer does, and all that you need. (Well, they also use a runaway detection circuit, so a single device can be characterized over many points, rather than destroyed for each.)
Mainstream MOSFETS are all about switching, and parts built for tough operation in linear-mode is a gray area. You have to wonder why IXYS actually has a lineup specifically for that.
Duh, marketing.
IXYS probably has a worse track record than most, on SOA capabilities. A lot of their HiperFETs
don't even have SOA curves at all. The ones that do, drop off terribly early (1ms curves, if that; certainly not DC). These are an exemplar of the previous generation: high power density, but high thermal sensitivity, too.
Now that they've licensed Infineon's CoolMOS, that's all in the past. I mean, not fully, as those product lines will take a decade to close out -- but you don't
have to buy them.
And, if you want the design assurance that they're actually intended for (and presumably, tested for) linear operation, you can buy those -- there's nothing wrong with that, you're just paying a premium for it.
So maybe a solution is to use several of the venerable IRFP460, for example, giving generous SOA derating.
Indeed, old MOS (like the above IR HEXFET family) tend to have crap power density, so they didn't reach into the region of thermal runaway, and are suitable for linear use.
They also have massive dies, perhaps unexpectedly for their price -- indeed, those ancient masks have fully depreciated and they cost almost nothing to make.
You can spend the same money on a new (SuperJunction type) part, and get only a third of the ultimate power dissipation (~die area). Point being, you also get about triple the switching performance (Rds(on) * Qg), or, even better than that, actually. Which is fantastic for switching, it just doesn't help us much for the immediate problem.
This leads to the next problem.
The reaction time of the current-limit circuit to discharge the MOSFETs' capacitance before the pulse SOA is exceeded... I think it's difficult with >10,000pF Ciss and the HV.
Have you... run the numbers on this?
Because, for a puny 2N3904 with 1k series base resistor, across a source current sense resistor, the response time is under a microsecond. I'm not kidding! Don't believe me?
Most of the circuits in this thread haven't even shown a base resistor (which is a rather unsafe proposition, I should add-), and so the delay will be in the hundreds of nanoseconds. About a quarter again, if it's a damn 2N2222.
Even going from hard saturation (say, Vgs(on) ~ 10V) to soft limiting, even with very pissy gate drive, doesn't take long, and it certainly doesn't violate the SOA.
It doesn't even necessarily violate the DC SOA, let alone the 10us pulse SOA.
Example: PSMN012-80BS with 50mohm source degeneration resistor, Vgs(on) = 9V, 40V step (t_r < 1us), -20A/div. This is another current limiting circuit I designed and built.
This is a 150W device (D2PAK, not that you'd ever be able to get 150W from it in practice), 100mJ avalanche energy so it's not a very big die (it's a newer generation -- not SuperJunction at this voltage, but nonetheless significantly improved from the IRFP days), and has a DC power limit of just a few watts in application (PCB cooling only).
https://assets.nexperia.com/documents/data-sheet/PSMN012-80BS.pdfFig.3 shows 10us SOA at 40V going well over 100A.
The pulse is
way under the limit, and that's with inferior gate drive. Qg(tot) is a lot lower than IRFP460, but a 2N3904 current limiter will pull down much harder than what's in this circuit, and in a
linear circuit, Vgs is already near Vgs(th) -- not all the way up at Vgs(on) -- so it only needs to shove the gate
a few tenths of a volt to do the job!
Don't cry
Miller effect, either -- that's included in the above pulsed test, of course (at the same time current drops from its peak, to the plateau value of 60-80A, drain voltage rises to the full 40V), and anyway,
don't argue from ignorance! Measure! Even SPICE will get this right!I hesitate to use single-slope SOA and the sense-resistor/transistor but maybe SPICE will say otherwise. The 470uF filter capacitor at 400V will dump some current into the MOSFETs for a usec or two, during a short circuit on the power supply's output. Let's be generous and add 10R series resistance. Down to 40A peak. Still a lot.
Where the fuck is 40A coming from, man? Really?
It's already in the linear range. It's drawing as much current as it ever will. Pentode curves at work here!
A step change in Vds will cause a step change in Vgs, yes -- this amount can be calculated or simulated, and the delta I_d found. It won't be 40A, and it certainly won't be V(B+) / Rds(on)!
And even if it were, 1us of that is perfectly within the SOA of any device that shows a square SOA on that time scale. For god sakes even IGBTs can handle that!
(Speaking of, and to reiterate: don't use IGBTs for linear operation. They have even less silicon than top-performance MOSFETs. They're made for switchin', and switchin's what they'll do.)
Application Note AN-1155 Linear Mode Operation of Radiation Hardened MOSFETS
AN-4161 Practical Considerations of Trench MOSFET Stability when Operating in Linear Mode
edit: forgot attachment
Incidentally, note that Trench MOS is a slightly newer generation than HEXFETs -- IIRC, HEXFETs are VMOS, and Trench was roughly the next gen after(..?!). The trench process has nicely served many designs, so you'll see the whole gamut, as far as stability and performance, in devices with that keyword. YMMV.
Tim