Logic-ICs - die pictures

[Noopy]

A minor mistake:
The DL003 is the variant with open collector output so it´s normal the highside transistor is missing. 

[Noopy]

The V40098 from the Funkwerk Erfurt contains six inverting drivers, which are combined in a group of four and a group of two. Both groups can be switched off individually. The characters V9 show that the module was manufactured in September 1987. With a supply voltage of 5V, the signal delay time is a maximum of 160ns.




The dimensions of the die are 2,2mm x 2,3mm.




The die is labelled U40098. The components with the letter V on the housing are specified for operation in the extended temperature range from -25°C to 85°C. The components with the letter U are only specified for operation between 0°C and 70°C. Binning was probably done after packaging.




The revisions of six masks can be seen in the bottom left-hand corner. The V4001 from the Funkwerk Erfurt (https://www.richis-lab.de/logic07.htm) and the V4001 from the Uhrenwerk Ruhla ("https://www.richis-lab.de/logic08.htm") show the revisions of seven masks.




The individual functional blocks are easy to identify. Protective structures are integrated in the outer area (pink/purple). The six identical structures of the six drivers are located in the centre of the die (green/blue and yellow/red). A smaller circuit is integrated on the left for activating the group of two (orange). A Bigger circuit activates the group of four (cyan).




The V40098 has the same protective structures at the inputs as the V4001 (https://www.richis-lab.de/logic07.htm). The V4001 contains a more detailed analysis of these structures.




In contrast to the V4001, protective structures have also been integrated between Vdd and Vss. These are definitely two diodes.




On closer inspection, the large push-pull transistors at the output can be clearly recognised. The activation signal is connected to the control circuit and is routed from driver to driver.


https://www.richis-lab.de/logic26.htm

 

[Noopy]

The U1525FC007 is a standard cell ASIC that was used in the Robotron A5105 educational computer. In this part of the documentation, only the structure and properties of the underlying standard cell design system U1520 are considered. A more detailed analysis of the functions of the U1525FC007 is provided in the third part of the documentation. The characters X8 stand for production in August 1989.




The U1525FC007 is based on the U1520 standard cell system. This was a development in the Zentrum für Mikroelektronik Dresden, which later became part of the Carl Zeiss Jena combine. In addition to the U1520 standard cell system, the U1500 standard cell system and the U5200 gate arrays were available. A lot of information on all three systems can be found in the document "Applikative Informationen 4/88" published by VEB Applikationszentrum Elektronik Berlin.

Each of the three architectures has advantages and disadvantages. Simple gate arrays such as the U5200 system contain a fixed arrangement of simple gates and flip-flops. More complex logic blocks are build with combinations of the available gates. To implement the desired functions, only the wiring levels are structured in an application-specific way. This means that the so-called masters can be produced with the same mask set and only a few application-specific masks remain. In the case of the U5200, there are 3 masks.

If you build a circuit with standard cell ASICs such as the U1500 or the U1520, you can use a relatively large number of different standard cells. These gates and flip-flops have a specific, optimized structure. As a result, they require less area and usually have better dynamic behavior. In addition, you can select exactly the number of elements you need and arrange them very freely. However, this also makes the development of such ASICs more complex. Production is also more complex because all masks are application-specific. In the case of the U1500, there are 9 masks. In the case of the U1525, there are 12 masks. What all architectures have in common is that the majority of the structures are known and tested. This simplifies the implementation of an application-specific circuit.

The U1500/U1520 system offers over 40 different standard cells and enables the integration of up to 13.000 transistors. In 1988, a price range of 30-300 Ostmarks was quoted. "Economically favorable quantities" would therefore be 1.000 - 100.000 per year. For the U5200 gate array system, on the other hand, there is an "economic upper limit" of 10.000 units per year.

The standard cell ASICs U1500 and U1520 are based on the CSGT2 process. CSGT stands for "Complementary Silicon Gate Technology". It is a 5V CMOS process with a minimum structure size of 4µm. The operating clock of the process is typically 4MHz, the gate delay is specified as 5ns. Two different variants of the CSGT2 process were used for the U1500 and the U1520. The U1500 is based on the CSGT2/N process, the U1520 on the CSGT2/S process. Although the dynamic parameters of the two processes are different, it is said that neither process can be described as better in this respect. The CSGT2/S just allows higher packing densities because the standard cells are smaller. However, the manufacturing process is more complex.

The successor generations to U1500 and U5200 were the U1600 and U5300 systems, whose minimum structure width is just 1,5µm and which have two metal layers. With even larger chip areas, the maximum possible number of transistors increases to up to 100.000. The operating frequency increases to 25MHz, the gate delay decreases to a maximum of 1,6ns. RAM, ROM and PLA areas were then also available in the U1600 system.




A little earlier, in the document "Applikative Information 3/88", there is a comparison of the advantages and disadvantages of the various product families. ...yeah, german language... 




The picture above shows the rational areas of application in a somewhat simpler way. Standard cell ASICs were considered particularly useful for medium quantities. The range of applications expands towards more complex circuits.




The "Fachbereichstandard" TGL 43876 describes how the standard cell ASICs U1500/U1520 were labeled. Unfortunately, however, the assignment of the description to the characters is slightly off. The designation U1525FC007 is explained as follows: U15 stands for this generation of standard cell ASICs. The 2 shows that the component was manufactured using the CSGT2/S process. The number 5 stands for the maximum chip size with an edge length of 7,5mm. F indicates that it is a ceramic package. The letter C indicates the usual operating temperature range. Finally, 007 is the specific type designation of the ASIC design.




Table 2 of the "Fachbereichstandard" shows which chip sizes were available in the U1500/U1525 system and in which housing types they were available.




The ceramic housing is easy to open.




The picture above shows the die of the U1525FC007 and is available in original size (34MB): https://www.richis-lab.de/images/logic/35x08XL.jpg




There are no inscriptions or symbols on the die. Only on the lower edge are the inscriptions of auxiliary structures visible in the remains of the milling line.




The structure of the U1525FC007 is typical for a standard cell architecture. The active elements are lined up in rows. The cells are connected between the rows via a polysilicon layer for vertical lines and within a metal layer for horizontal lines. The supply voltage is fed in at the side. If circuit parts that are further apart need to be connected to each other, the area between the standard cell rows and the bond frame can be used. This is also where the lines run between the interfaces in the bond frame and the inner circuit parts.

However, the standard cell ASICs did not necessarily have to adhere to this clear architecture. In the U1500PC050, the circuit parts are arranged more individually and have been supplemented with very individual structures: https://www.richis-lab.de/phone03.htm




The document "Applicative Information 4/88" describes how standard cell ASICs were developed. Once the user has defined his logic circuit, the placement and connection of the cells can be done automatically.




According to "Applikative Information 4/88", in the U1500/U1520 system you can choose from a catalog of 43 standard cells. There is a standard cell catalog from which one page is shown. Unfortunately, the complete catalog is not publicly available.

Each standard cell has a name, here "ANO 24". In the top right-hand corner you can see in which process this cell is available. Below this is the associated symbol, the mathematical description and a textual description of the behavior. When designing the layout, the standard cells are represented by rectangles with the respective symbol. The entire layout is divided into grids. The standard cell shown here takes up 7x5 or 8x5 grid cells. The description of the cell shows which interfaces are available at the top and bottom edges.

The gate equivalent makes it possible to estimate the area required for the circuit. A gate is assumed to have four transistors. Accordingly, the ANO 24 gate requires the area of eight transistors.

Finally, the lower section contains the parasitic capacitances of the inputs and the permissible capacitive load of the output. These figures give the maximum permissible number of gates that can be connected to an output. Line capacitances must be added too. The values apply to the typical operating frequency of 4MHz, at lower frequencies, more gates may be connected to an output. The upper limit is 50 gates. The delay of the cell is also defined.




An early standard cell catalog from 1983 is publicly available on the website of Dr. G. Heinz. However, this catalog only documents the possibilities of the U1500 ASICs based on the CSGT2/N process: http://www.gheinz.de/publications/berliner_ics/index.htm#35

The description of the cells is somewhat more detailed in some cases. The first page contains both a circuit diagram and the gate width of the transistors. The second page shows the corresponding structures as found on the die.

This document also states that it was possible to define new standard cells. The new cells must then be agreed with the publishers.




The layout data for the U1520PC201, another U1520 variant, can be found on Dr. G. Heinz's website: http://www.gheinz.de/publications/berliner_ics/index.htm#slic-b

The standard cells are shown as rectangles with the corresponding symbols. The labeled inputs and outputs can be found at the upper and lower edges. The elements have different widths. Flip-flops are slightly higher than standard gates. The necessary input and output blocks are located in the bond frame. Between them, lines in the polysilicon layer and in the metal layer provide the necessary connections.




In the real circuit, the cells are much harder to make out, but with a little practice you can easily recognize the transitions from one cell to the other.




The standard cell catalogue is only available for the CSGT2/N process. Although the CSGT2/S process offers almost the same standard cells, the structures are clearly different. If you know which cells to compare, you can recognise some similarities in a direct comparison. However, this is not sufficient for a simple identification of the cells. For this reason, it is necessary to understand the function of each individual cell. However, knowledge of the basic technology and the logic blocks available is very helpful.




The CSGT2/N standard cell catalog shows the masks used. There are 10 masks listed, but the n+ channel stopper was not necessary, as Dr. G. Heinz explained in detail in 1985: http://www.gheinz.de/publications/berliner_ics/index.htm#18

This results in the 9 masks already described for a relatively simple CMOS process. When looking at the gates, it is immediately apparent that the U1520 is more complex. A second polysilicon layer can be recognized. This matches the 12 customized masks attributed to the U1520 system. This would be a mask to structure the second polysilicon layer. One mask for the contacts to the layer below and one mask for the contacts to the layer above.




The supply lines are located above and below the logic lines in the metal layer. The metal layer (blue) is mainly used for the power supply and signal forwarding between the standard cells. However, it is also partially used within the cells.

The second polysilicon layer added in the CSGT2/S process is only used inside the standard cells (green). It enables the higher integration density and explains the significantly different architecture compared to the U1500. The frame color of the arrows shows on or under which layer the respective layer is located at this point. The visual appearance often changes.

The lower polysilicon layer (pink) is somewhat more finely structured than the upper one. It also represents the gate electrodes. The lower polysilicon layer also provides the contacts to the wiring area. The structures of the polysilicon layers can be seen reasonably well through the metal layer. However, if the edges of the two polysilicon layers cross underneath the metal layer, it is often difficult to identify the conductor routing.

The active areas (white) are located under the other structures. The corresponding edges are clearly visible. At these points, windows have been etched into the thick silicon oxide that otherwise covers the entire wafer ("field oxide"). Transistors only form in these windows when a strip of the lower polysilicon is applied to them.

The active area and the three wiring layers cannot be connected to each other at will. The contacts between the second polysilicon layer and the active area (red) and between the first and second polysilicon layers (orange) are clearly visible. The metal layer can obviously only contact the second polysilicon layer (yellow). If you want to contact the first polysilicon layer or the active area with the metal layer, this must be done via the second polysilicon layer. This sometimes results in contacts that lie on top of each other and areas that appear more complicated than they should be at first glance.




The active areas are always divided into at least two parts. In the upper areas only p-channel MOSFETs are located (red frame). In the lower areas only n-channel MOSFETs can be found (blue frame). The active areas are connected at several points with Vss (blue areas) and Vdd (red areas). In this cell, the Vss contact in the lower left corner is somewhat unclear. This is due to the extended use of the second polysilicon layer. The rectangular contact connects the metal layer with the second polysilicon layer. This then extends to the right and upwards and is connected to two surfaces of the active area via two round contacts.

In the image on the right, the surfaces of the first polysilicon layer are marked in color. Common potentials have the same color. Where the polysilicon covers the active areas, a transistor is formed. The different contact possibilities at the top and bottom edges of the standard cell are clearly visible.

The connections via the second polysilicon layer and the metal layer are marked with dashed lines. Approximately in the middle of the cell there is an area where it is very difficult to assign the contours ("?"). At such points, you have to work with the background knowledge of existing logic functions or record parts of the circuit in order to be able to draw conclusions about the rest.




With the knowledge of the structure and function of the structures, you can finally mark the transistors. Recognizing the circuit is easier than it appears at first glance. Firstly, it is known which logic gates must be present and secondly, the circuits usually only consist of relatively simple parallel and series connections of transistors.

This is an EXOR gate containing five p-channel and five n-channel MOSFETs. The circuit diagram is taken from the standard cell catalog of the U1500. Proper documentation of the standard cells and their contacts is extremely important for further analysis of the circuit.


https://www.richis-lab.de/logic27.htm

 

[Noopy]

I have updated the first part of the U1525FC007:

- I have flipped some of the pictures so we have Vss in the lower areas of the pictures and Vdd in the upper area of the pictures. That is probably more convenient for everybody.

and

- I have added a comparison picture with the layout shown in the CSGT2/N standard.


The upper Post is updated due to hotlinking and editing... 

[core]

I have updated the first part of the U1525FC007:

- I have flipped some of the pictures so we have Vss in the lower areas of the pictures and Vdd in the upper area of the pictures. That is probably more convenient for everybody.

and

- I have added a comparison picture with the layout shown in the CSGT2/N standard.


The upper Post is updated due to hotlinking and editing... 

Very interesting information ! Thanks for sharing.

[Noopy]

Basis for analysing the standard cells used in the U1525FC007 is the list in the document "Applicative Information 4/88". The relatively old standard cell catalogue for the U1500 represents only a subset of the available cells, but it is helpful because it also contains the circuitry of the respective cells. In the U1525FC007, 21 different gate types and 3 interface blocks were used.




The negator or inverter, NEG1, is the simplest gate. It merely inverts the input signal. This behaviour is self-evident if the input signal is used to control a push-pull stage consisting of a p-channel MOSFET (red) and an n-channel MOSFET (blue).

As only two transistors are required, the corresponding cell on the die is very narrow. The input signal contacts a polysilicon strip that runs across two active areas. On the right, these are connected to the supply potentials. On the left-hand side, the second polysilicon layer contacts both transistors and the output signal generated there is led out upwards and downwards. A small metal contact would also make it possible to tap the output signal in the cell via the metal layer. Such metal contacts, which could be used to connect the various gates, can be found in many standard cells. However, they are never used in the U1525FC007.

In his 1985 lecture, Dr G. Heinz explains that in the CSGT2/N process, a connection between the polysilicon and the active area is only possible via a metal island. (http://www.gheinz.de/publications/berliner_ics/index.htm#18) Of course, this could also have been the case with the CSGT2/S process of the U1525-FC007 and would then be an explanation for the unused metal contacts. However, the circuits and the associated layouts show that, as described, the metal layer can contact the upper polysilicon layer and the upper polysilicon layer then contacts the lower polysilicon layer or the active area.




The clocked inverter bears the abbreviation NGT. It is an inverter that is extended upwards and downwards with additional transistors. The additional transistors use the clock signal to control the forwarding of the signal. Like most clock-controlled gates, the clocked inverter also requires a complementary clock signal in addition to the clock signal.

The real implementation is more complex, but still clear. Here too, the output signal is also applied to a small metal island located in the centre of the cell.




The TRIS cell is an auxiliary circuit that is used to control outputs that also enable a tristate state. It is a combination of an inverter, a NAND and a NOR gate. If a high is present at control input Z, output AP remains high and output AN remains low regardless of the status at signal input E. Otherwise, the outputs pass on the current level of the signal input. In this cell, the metal layer is used more often, which makes it much more confusing.




In the ANO24 cell, two AND gates are combined with an OR gate. Here too, the output potential is additionally connected to a metal island within the cell.




In the ANO4 cell, an AND and an OR gate are combined with a NOR gate.










The NAND gates NA2, NA3, NA4 and NA6 are very clearly structured. The variant with six inputs is only available for the NAND gates, not for the NOR gates.




An EXOR gate requires a relatively large number of transistors compared to a NOR gate.




The ONA24 provides the user with a further gate combination. In this case, there are two OR gates that are combined via a NAND gate.




The ONA3 is a simpler gate combination. This is an OR gate that is surrounded by a NAND gate.








Like the NAND gates, the NOR gates are very clear.




The ES block is a simple input that behaves like an inverter. With the ESH and ESL blocks, there are additional inputs that also forward a defined signal in the unconnected state.

There is a protection circuit at the bondpad, consisting of a diode to the Vdd potential and a diode to the Vss potential (pink/green). A strip of the active area forms a resistor that serves as a current limiter (yellow).

On the right are the p-channel and n-channel MOSFETs, which act as inverters for the input buffer. It is interesting to note that the n-channel MOSFET is twice as large as the p-channel MOSFET. This is unusual. The p-channel MOSFET is usually larger because it has poorer properties.




The simple push-pull output is labelled AS1. To the right and left of the bondpad is a whole row of p-channel and n-channel MOSFETs, which can provide the necessary current delivery capability.




The BDL interface is bidirectional and offers a tristate state. For this purpose, the gates of the large output transistors are led out individually. They are usually controlled via the TRIS cell.

A line also leads from the bondpad to the input circuit in the upper area. The familiar protective structures are integrated on the right and left. The transistors of the buffer inverter are located between them. Here too, the n-channel MOSFET is surprisingly large. The L stands for the fact that the block outputs a low level when the input is not connected. An additional p-channel MOSFET is integrated for this purpose, whose gate is connected to the Vss potential and thus represents a pull-up resistor at the input.






The DFFR cell is a master-slave D flip-flop with reset input. The circuit consists of 12 p-channel and 12 n-channel MOSFETs and occupies a correspondingly large area. All master-slave flip-flops are slightly higher than the normal gates to enable a sensible arrangement of the elements.

Here, both the output signal and the complementary output signal, as well as the clock signal and the complementary clock signal can be contacted via the metal layer in the centre of the cell. The lines were also routed to the side edges, presumably to enable simple cascading. These contacts were never used in the U1525FC007.






The master-slave D flip-flop with set and reset input, DFFRS, is the largest standard cell found in the U1525FC007. The circuit does not quite correspond to the circuit diagram. However, the differences are hardly relevant. As in the DFFR cell, the transistors connected to the clock signal are located on the outside, near the supply potentials.






The master-slave D flip-flop with set input, DFFS, is very similar to the DFFR cell.




The LFF cell is a simple D flip-flop. In contrast to the master-slave flip-flops, the normal cell height is sufficient here.




A simple D flip-flop with set input is also available under the designation LFFS.




The RSNA cell is an RS flip-flop. It is an interconnection of two NA2 gates.




Some of the standard cells have been additionally mirrored.




The U1525FC007 contains 1.001 gates using a total of 6.902 transistors. Excluding the gates in the bond frame, 935 gates were used.


https://www.richis-lab.de/logic28.htm

 

[Noopy]

There is no datasheet for the U1525FC007. The module was specially developed for the Robotron A5105 educational computer. A circuit diagram of this computer system can be found on Ulrich Zander's website: https://www.sax.de/~zander/bic/bic_hw.html This allows you to recognise the approximate functionality of the pins and the circuit.




The freeware Inkscape is ideal for analysing the U1525FC007. It allows you to conveniently place and manage a large number of symbols and texts on the die.




In the first step, the bondpads are labelled with the pin designations from the circuit diagram.






In the second part of the documentation, all gate types were identified. Ideally, all gates should be marked on the die in this step. Here, a square was placed around each gate. Inkscape links a consecutive number to the square. The different colours stand for different gate types. If you create folders for the different gate types, this will make it easier to find them later.




The next step is to mark all signals that arrive at the U1525FC007 or are transmitted to the outside. Different colours and collective folders also provide a better overview here. This preparatory step is not absolutely necessary, but it makes it easier to analyse the circuit further.

Prominent signals can be marked one or two levels deeper in the circuit. For example, the reset signal passes through several inverters, partly to distribute the capacitive load of the many receiver gates and partly to generate an inverted signal. The display of a double inversion appears unnecessary at first glance, but indicates that this signal is slightly delayed compared to the original signal.




The die marked in this way serves as the basis for further analysis of the circuit.




Various programmes can be used to document the circuit. KiCad was used here. KiCad is actually used to create circuit board layouts. I think everybody here knows it.  However, the circuit diagram editor is also suitable for documenting logic circuits. The 24 standard cells of the U1525FC007 must first be added to the component library.

Minor peculiarities, such as the descending numbering of the inputs on the NOR gates, resulted from initial errors in the analysis, which only became apparent after the circuit diagram was created. In order to keep the change effort within reasonable limits, such cosmetic peculiarities were accepted.




KiCad numbers the gates automatically. This designation is used in Inkscape as the name for the corresponding rectangle. This allows you to find a gate in Inkscape later. It is also easy to see which gates have already been included in KiCad. In addition you can fill the rectangles with 50% transparency black. This makes it easier to analyse because you can immediately see whether a line leads to a known gate.

The fully marked SVG file is stored here (174MB): https://www.richis-lab.de/images/logic/35x57.svg




The circuit is best recorded from interfaces whose downstream functions are known or at least can be surmised. If, after a certain amount of time, you can't get a feeling for how the local part of the circuit is developing, you should switch to another part of the circuit. When documenting the circuit, you will gradually gain an understanding of how it works and you can arrange and group the gates in KiCad in a sensible way.


https://www.richis-lab.de/logic29.htm

 

[Noopy]

The interfaces of the U1525FC007 can be extracted from the circuit diagram of the Robotron A5105 educational computer. The module is connected to the 8Bit wide data bus and receives the clock signal and the reset signal, which is also used by the processor. The processor is a U880, which is functionally equivalent to a Z80. The U1525FC007 receives some control signals directly from the processor, from which it generates the MWAIT signal, among other signals. Nine address lines are processed from the 16-bit wide address bus. The module checks the keyboard or joysticks and generates the sound. The U1525FC007 also supports the U880 in the selection of various function groups: ROM, RAM, optional plug-in cards, PIO and CTC module, graphics unit and an optional cassette drive.




The papers presented at the 13th Microelectronic Components Symposium (Volume 7) contain some information on the U1525FC007. There the designation U1520-FC-007 is used, in which the chip size is missing. In addition to the abbreviation SVG, the component is also described as a "circuit for memory management and sound generation". The printed block diagram matches the integration in the Robotron A5105.
Like the Z80, the U880 can control a maximum memory volume of 64kB. The U1525FC007 extends the address table. The Robotron A5105 contains two EPROMs with a volume of 32kB and 8kB. There are also two DRAM modules, each with 32kB. The memory can be expanded using plug-in cards. The Microelectronic Components Symposium mentions 256kB of RAM. It is more plausible that the memory area can be expanded to a total of 256kB. The RAM may then be a maximum of 192kB in the A5105.




The logic in the U1525FC007 has been completely transferred to a KiCad circuit diagram. The use of only one sheet simplifies the creation of the logic circuit, as you can work more creatively. In addition, there are very large circuit blocks, the division of which would have an unfavourable effect on clarity. The thick blue frames represent a demarcation of self-contained function blocks. The block diagram from the 13th Microelectronic Components Symposium was not yet available here, which is why the layout of the circuit is not based on it. However, the block diagram is fully consistent with the extracted functions.
The KiCad file can be downloaded here: https://www.richis-lab.de/images/35x64.kicad_sch (2MB). Such large graphics cannot be packed into common image formats such as JPEG. An SVG file is available here: https://www.richis-lab.de/images/35x83.svg (14MB). It can be opened and edited in Inkscape.
The following relationships and functions have been extracted and documented as good as possible. However, it is quite possible that minor errors have crept in, individual addresses are not quite correct or potentials have been inverted.




Some interfaces can be used as a starting point for the documentation of the circuit. These include the address bus, for example. The global identifiers outlined in red are the interfaces to the outside, i.e. the bondpads. Internally, most connections are shown as continuous lines. Only some highly branched potentials, such as the address bus, are distributed on the circuit diagram with so-called hierarchical identifiers. The address bus first passes through the input gates. Most address lines are also inverted for further use.
Further global signals are collected on the right, for example the read and write signals. The reset signal serves a total of 55 gates. The large number is probably one reason why five inverters pre-process the signal. The clock signal only serves seven gates, yet three inverters have been integrated here. The requirements for signal integrity were probably higher than for other signals. In the Robotron A5105, the PM potential is connected to the 5V potential via a pull-up resistor. The function of this potential will be considered in more detail later.




The data bus is routed to bidirectional interface gates with tristate function. These interface gates are controlled via TRIS gates. The /OUT_EN signal controls whether data may be placed on the data bus or whether the current potentials are to be read in. Clocked inverters are used to read in the data. An internal data bus is generated from this circuit.




A function block controls the addressing of the memory areas. SL0L and SL0H each activate one of the two EPROM modules. S1 and S3 can be used to select the two interfaces for optional modules. The selection of the two 32kB RAM modules is controlled via CAS and WSMUX. Everything is controlled via the internal control signals S1 and S2.
The second function block generates a whole series of control signals based on the address lines and the control signals of the U880. In addition, the interrupt output of the PIO module is analysed. The read and write signals for the graphics unit, which also serve as selection signals, are output directly. The selection signals for PIO and CTC are also output directly. The DIR signal defines the flow direction of the data transceiver at the connectors for the optional modules. The WAIT signal is used to signal to the processor when the addressed resource is available.
The right-hand function block also generates some internal control signals. One of these enables data to be transferred to the data bus. Further control signals can be used to transfer data to the internal registers. In the presentation from the Microelectronic Components Symposium, two of the registers are labelled Port A and Port C. Port A is written in parallel. Port C can be written in parallel or serially via two control signals. The integrated sound generator has very extensive configuration options. The register to be written to is selected via a control signal. A second control signal can then be used to write to this register.




The control signals SL0L, SL0H, SL1, SL3, WSMUX and CAS are selected by linking the internal control signals S1 and S2 with the control signals of the processor. S0L and SL0H are also dependent on address bit A15.
WSMUX and CAS also have flip-flops which ensure that the address of the processor is split into row and column selection. If MRQ is active, the RAM immediately takes half of the address as row selection. If the RAM is selected, the circuit in the U1525FC007 ensures that the second half of the address is switched through to the RAM with WSMUX and this part is subsequently adopted as column address with CAS.
At first glance, it seems strange that the row selection in the RAM always takes place, even if the RAM is not selected at all. This transparency is necessary so that the DRAM can be refreshed, which the U880, like the Z80, carries out automatically. As the DRAM only outputs data on the bus with a column address, the selection of a row address alone does not lead to a bus collision.






The decoding of the control signals is quite clear. The links between the addresses and the control signals can be easily extracted. While MRQ indicates an access to the memory area, the processor uses IORQ to communicate an access to a peripheral circuit. The signal M1 belongs to such an interrupt cycle.




The generation of the DIR and MWAIT signals can be seen here. The U1525FC007 only inserts a fixed delay between the start of a memory interaction and the positive feedback via MWAIT.




The Port A register can be used to configure the addressing of the memory areas. The current value of the data bus is saved in port A with the corresponding control signal. The stored value can also be read out.
Depending on which of the eight bits are set in port A, different combinations of address bits 14 and 15 are required to activate the control signals S1 and S2. Various combinations do not make sense. In all probability, only two bits are ever set in port A. Combinations that activate S1 and S2 with the same address combination also appear to make little sense and are painted grey here.




The Port A register is build with DFFR flip-flops.




To be able to select a memory area, RFSH must have a high level and MRQ a low level. This means that there is no refresh cycle active and the processor wants to access a memory. The control signal combinations 01 and 11 can be used to select the interfaces of the optional plug-in cards (SL1/SL3). 10 activates WSMUX / CAS and thus the interface of the RAM modules.
SL0L and SL0H, the two EPROM modules, are only active if no bit is set in the Port A register. This appears illogical at first glance, as no other memory area can be activated in this state. Port A must first be rewritten. However, this implementation has the advantage that the EPROMs where the program is located can be accessed immediately after a reset without initialising the SVG. By linking to address bit 15, the control of the EPROM initially appears completely transparent to the processor.




A multiplexer makes it possible to place various data on the data bus. One data source is the TB* inputs, which show the processor which key on the keyboard is pressed. Alternatively, the data in the Port A or Port C registers can be placed on the data bus. One of the three data sources is selected via the address lines A0 and A1.
The data register Port C can be loaded with data in parallel or serially. The content of the register controls the line selection of the keyboard logic (TA*), the cassette recorder, the caps lock LED and the signal for the key tone.




Here you can see a part of the multiplexer.




The Port C register is constructed with DFFRS flip-flops. The register can be loaded in parallel via the D inputs. Serial loading takes place via the set and reset inputs. The underlying logic evaluates the level of data bit 0. Data bits 1 to 3 define which bit of the register is to be written.




The sound generator takes up a lot of space in the U1525FC007. The configuration registers account for a large proportion of this. There are 16 registers with a total of 83 bits.




The sound generator integrated in the U1525FC007 is very similarly to the AY-3-8910 sound generator from General Instrument. Even the control registers have the same structure and arrangement. The U1525FC007 only lacks the Port A and Port B interfaces and the mixer at the output mixes the signals into a single channel. In addition, the digital-to-analogue converter is located externally.




Four LFFS flip-flops use the first four bits of the data bus to select a line of the configuration register for the sound generator.




With some additional logic, the LFFS flip-flops generate the clock signals for LFF flip-flops, which represent the configuration registers themselves. The inputs are connected to the data bus. One address triggers the LFFS flip-flops and thus the line selection. Another address then allows the LFF flip-flops to accept the data on the data bus.




The sound generator is based on six clock dividers. The 3,75 MHz basic clock of the A5105 can first be divided down by a factor of 16 before it is then passed to the five other clock dividers as a working clock.
One clock divider defines the basic frequency of the noise generator and can divide the working clock by 2 to 2^5. A further clock divider generates the clock for the amplitude modulation with a divider factor of 2 to 2^17. The three tones that the sound generator can supply are generated via three clock dividers, each with a divider factor of 2 to 2^13. This results in a frequency range from 28Hz to 117kHz.




The clock dividers are based on DFFRS flip-flops. Their exact mode of operation only becomes apparent at second glance. The circuit not only takes up a lot of space on the circuit diagram, but also on the die.
The interfaces PM, OP0, OP1, OP2 and OP3 appear to be used for diagnostic purposes. The frequency dividers of channels A, B, C and the envelope generator are divided into groups of six and one group of four. This results in nine groups that can be read out individually. The selection signal for register 0010 switches the four OP outputs, making it possible to reach eight of the nine groups. The PM input can be used to isolate the groups from each other and feed them with the same clock signal. The PM signal also switches the remaining group to the S0H output.




The sound generator contains a noise generator that also uses a divided clock frequency.




Of course, this is only a pseudo-noise generator that does not really generate random noise. There are 20 DFFS flip-flops connected in series. The input signal is generated by an EXOR gate, which links the current output signal with the output signal of the third flip-flop. This results in a pseudo-random output signal.




The envelope, i.e. the amplitude modulation of the output signal, can be defined with a further circuit section. The basis here is also the divided working clock.




The datasheet of the AY-3-8910 shows which envelopes can be generated. The circuit itself is rather confusing. It feeds four data lines, the value of which represents the current amplitude.




The configuration register ultimately defines which of the three tones is forwarded. Each tone can be linked to the noise signal or just the noise signal can be forwarded. The three signals then pass through an amplitude control, which can be set via the configuration register and is also modulated with the generated envelope function.




Here you can see the circuit for one channel. The tone or the noise signal or both signals are selected in gate U817. The NOR gates on the far right pass on the signal if the ANO24 gates in front of them allow this. The amplitude configuration and the envelope information are linked in these gates. The four outputs all carry the same signals when they are active. Depending on which of the outputs are active, different amplitudes will result later.




The functionality of the sound output becomes clearer if you take a look at the circuit diagram of the A5105. There, a resistor chain represents a discrete DAC. Each S output serves an inverter, which influences the output level more or less depending on the connection point.




Before the sound signal is delivered, a mixer combines the three generated channels.


https://www.richis-lab.de/logic30.htm

 

[iMo]

FYI - a silicon-on-sapphire die..
https://www.righto.com/2023/12/HP-silicon-on-sapphire-phi-chip.html

[Noopy]

Yeah, that´s cool. I have an old and very special HP die here and thought it was SoS too. It had a strange colour but unfortunately it´s not SoS.