Logic Compatability Question: SPI Interface

[bhj99]

Hi all, I would like to get opinions on whether or not I need a level shifter (translator) device for a board design.

The interface under question is the standard 4-wire SPI interface (MISO, MOSI, SCLK, CS*, and SCLK = 25 MHz) between the Microchip MFPS095T FPGA SoC and the Atmel RF transceiver AT86RF215. I will be configuring I/O on the microprocessor subsystem on the FPGA to support SPI using the LVCMOS33 I/O standard (FPGA bank VDD = 3.3V). On the AT86RF215, VDD = 3.0V as recommended on the datasheet. The power supplies that I am using have a worst-case tolerance of +/- 2.5%. Will I run into issues if I simply connect the SPI lines directly between the two devices? After doing some quick VIH/VIL, VOH/VOL calcs, I believe there is enough margin where I would NOT need level translators, but I could be wrong and miss something obvious, espeically with high-speed interfaces. Any thoughts? Appreciate any input!

Pages 16 & 17 give the DC Input/Output levels for the FPGA (LVCMOS33): https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/DataSheets/PolarFire-SoC-Datasheet-DS00004248.pdf

Page 187 gives the digital pin characteristics of the AT86 RF transceiver:
https://ww1.microchip.com/downloads/en/devicedoc/atmel-42415-wireless-at86rf215_datasheet.pdf

[Howardlong]

That AT86RF215 shows operating range DEVDD/EVDD digital and analog external supply voltages of 1.8 to 3.6V, table 10.1.

For the MFPS095T, GPIO aux Vdd looks the most stringent, between 3.135 and 3.465V, table 3-2.

Why wouldn't a standard 3.3V for both devices work?

The way I dealt with exactly this mismatch in one of my designs was to use a 3.15V regulator, TPS799315 in my case. which was chosen for its low noise and high PSRR in my mixed signal application, as one device was 3.0 to 3.6V and the other maxed out at 3.3V, so I picked the happy medium.

[bhj99]

Fair point, 3.3V could be used. However, I want to use a separate low-noise LDO just for the RF circuits, as my 3.3V rail powers a lot of digital circuits, including FPGA, and the AT86RF215 datasheet calls out 3.0V typical, so I wanted to follow that. Do you see issues with the SPI interface when separate 3.3V/3.0V supplies are used?

[ataradov]

This is absolutely not necessary. I don't know where that recommendation came from, but everyone uses standard 3.3 V. You are creating more problems for yourself for no reason at all.

[SiliconWizard]

While the 3.0V -> 3.3V direction should be no problem (you'd be way above the min threshold for VHigh), the 3.3V -> 3.0V direction may tickle the internal clamp diodes on the AT86RF215. Probably not enough to cause any damage, or not at all if you're lucky.

But as suggested already, using the same voltage would be easier. If you absolutely want to power the AT86RF215 with 3.0V, you could power the corresponding FPGA IO bank with 3.0V as well and call it a day (unless you share the same bank with IOs that must absolutely be 3.3V).

[bhj99]

Thanks for the feedback, everyone. It would be easier to just power both both devices at 3.3V and just save the headache.

[Howardlong]

Fair point, 3.3V could be used. However, I want to use a separate low-noise LDO just for the RF circuits, as my 3.3V rail powers a lot of digital circuits, including FPGA, and the AT86RF215 datasheet calls out 3.0V typical, so I wanted to follow that. Do you see issues with the SPI interface when separate 3.3V/3.0V supplies are used?

Coincidentally, that was my precise scenario too, an RF + baseband power domain, and the digital domain.

The analogue power domain and digital power domain were powered by two separate low noise, high PSRR LDOs. There is also SPI running to the RF section.

As an aside, it was also possible to completely shut down the analogue side to save power, placing the SPI lines into Hi-Z too of course.