Thanks for hanging in here with me, I think I am making progress.
VBUS is connected and is stable 3V3. I have a testpoint.
I will share the screenshots if you really want them in a minute, but I need to confess that I'm an idiot.
The bootloader AN2606 tells me this: The STM32F105xx/107xx bootloader is activated by applying Pattern 1 (described in Table 2).
Table 2 tells me: Boot0(pin) = 1 and Boot1(pin) = 0
Boot1? The symbol doesn't have a Boot1...
The datasheet tells me: G5 28 37 PB2 I/O FT PB2/BOOT1
For this part, that means that pin 28 can be overloaded with BOOT1.
Oh. What is pin 28?
The schematic tells me: X
What I have done for the last couple of hours has been to set aside my normal duties and hook up the JLink. I can connect to the board via SWD! I can read registers, halt the CPU, reset it, read memory... And the PC is in SRAM. Why is it in SRAM? That much is probably obvious from the above.
I cannot read the bootloader memory or the config data. I assume that when the device is not booting from the bootloader that this region of memory is not mapped.
Fair enough?
Time for another board spin?
Yes. I'm not entirely sure what QOL changes I could put on here to help debug. That SWD connector was worth its weight in gold.
And yes, I am an idiot.
But I'm doing better.