Layout: LVDS on top layer?

[Pack34]

I'm working with a new sensor that will send LVDS data from a sensor to an FPGA. I believe that you would typically route these on internal layers to mitigate crosstalk, however, the routing is less than half an inch. Would it be safe to keep the traces on the top layer? Or do I really need to dodge down to an internal layer for that half-inch?

[fourtytwo42]

IMOP better to avoid the impedance disruption through the via's as long as the next layer down is a solid referance plane under the micro-strip and either side of it. Of course you will have to calculate the impedance according to the deilectric thickness.

[ejeffrey]

Its fine to run LVDS on the top layer.  You just need to make sure your impedance is correct and the lengths are matched.

[NiHaoMike]

My Digilent Atlys has quite a few LVDS pairs running on the top. As it's a differential signal, EMI is much less of a problem.

[T3sl4co1l]

Its fine to run LVDS on the top layer.  You just need to make sure your impedance is correct and the lengths are matched.

Heck, with a run that short, even that won't matter, at least unless it's gigabit and time-critical.

Tim

[Pack34]

Its fine to run LVDS on the top layer.  You just need to make sure your impedance is correct and the lengths are matched.

Heck, with a run that short, even that won't matter, at least unless it's gigabit and time-critical.

Tim

Only 300Mhz.

Thanks guys!