Routing qspi flash memory to work 120MHz

[jealcuna]

It is my first time routing a qspi flash memory to work with 120 mhz in order to get 480mbps. So I place the chip as close as possible, but I am not sure if the length difference between io lines, clk and cs will be a problem.

I attach a picture of my design.

[ataradov]

This looks fine. The traces are short enough. If you are worried, add a bit of a length on the IO0 line - just fill the space between it and SCK line. But even that should not be necessary here.

[Benta]

Looks fine to me as well. Don't worry.

[jealcuna]

Thank you very much 

[jealcuna]

So I was reading some references design from cypress and modify the pcb like the picture attached. I hope don't make worse the simple first design

Now every io trace has the same length to clk line. I read that sometimes is necessary to route with impedance matching tracks.

[langwadt]

I don't know if length is that important at 120MHz but if so I'd be more concerned about vias/no vias

[Cerebus]

Velocity of propagation (as a velocity factor) in a transmission line is \$ \frac{1}{\sqrt{{\epsilon}_r}} \$ where \$ {\epsilon}_r \$ is the dielectric constant, which for FR-4 pcb material is about 4, so the velocity factor for FR-4 is 0.5, so signals will travel across the PCB at ~150 Mm/s. So 1mm of track length difference is going to be 6.7 ps. Look at your timings and I think you're see that a few mm is going to be neither here nor there. Your half clock time is 8.33 ns, 1250 times shorter than the slew due to a 1mm delay. So you're good, by a long way as far as length matching is concerned.

[langwadt]

https://www.cypress.com/file/196526/download

[ataradov]

Yes, if anything I would be more worried about the vias. See if you can pass the IO3 trace between CS and IO1 and route it that way on the same layer. Or route it over the CS signal and jump the CS to the other layer, as it is not so sensitive to timings.

Also, you CS does not seem to be connected anywhere.

Length matching does not matter as much, but there is no harm in having it.

[jealcuna]

Ok, so my final design is attached.

io3 now have 7 mm more than the others signals. Following the equation of Cerebus, (6.7ps * 7) = 46.9ps for extra delay. For 120Mhz freq clock a 8.33ns represent 178 times the delay generated for 7mm of extra length.

I assume that if the clock freq is 100 times bigger than extra delay there is no problem, isn't it?

Thank you very much to all of you guys.

[TiN]

Also ensure there is solid ground plane under chip and this routing, so you get nice uniform impedance response for high-speed. Any reason why passives are so large (0805?).

[jealcuna]

Yes, I had plane ground right after front layer.

Sometimes we assembly pcb by ownself. So 0805 is friendly in pick and place process.

[ataradov]

This is fine. 7 mm is not significant. But I would either use the free board space to better length match the reset of the traces, or remove the matching entirely. Both options are fine, but since you already went into trouble of putting the matching in, just do it for style points.

[jealcuna]

Like this?

I am not sure if this is correct because of serpentine clock. Cypress guideline recommend a straight line.

[ataradov]

This looks like you moved the whole chip away to fit the serpentine. Don't do that. Just straighten the lines if they don't fit and require moving components around. 

[jealcuna]

Ok, I will take in consideration. In this case I had extra space so, I did not have to move components. I still having doubts about serpentine clk

[DavidAlfa]

Thats a nice over-engineering there! I'm not expert here, but that's overkill.
If you check existing layouts, you'll see length matching done on much faster signals or longer traces.
In your case, don't worry, it's perfect as it was, compact and tidy.