Oh and as for reduced supply -- yes, it will just pass input to output, minus the dropout voltage. Which is poor for 7805, but proper LDOs are fine.
The two gotchas for LDO selection are:
1. check for ground or ADJ pin current. Preferably find a plot of Ignd vs. Vin for given Vout and Iout. Normally, it is low at low voltages, rising to a modest peak (perhaps 2x the stable value) near dropout, then falling to the rated (stable) value for Vin > Vout + Vdropout. The catch is, some PNP type LDOs didn't handle saturation properly, and could draw 10s of mA in dropout as they vainly fight to keep the output voltage up. Newer types should be clear of this behavior, and CMOS types should be pretty low current in general.
2. Stable capacitive load. Older LDOs especially were designed for capacitors with significant ESR (electrolytic and tantalum); they are wholly unsuitable for ceramic bypass capacitors and oscillate madly with them. Look for a stability region plot, typically showing C and ESR along the axes. Failing that, look for phrases such as "stable with ceramic capacitors" or "very low ESR"; these are unfortunately less specific, but if they can be believed, it should be fine.
As for gate drivers at low voltages, you can shop around for drivers with specific UVLO (undervoltage lockout) -- they won't turn on until sufficient VCC is present. Most are around 5V I think, which is pretty marginal for high voltage types, but quite adequate for lower and logic-level types. I would be quite comfortable with an 8 or 9V threshold.
Mind, they're all made for N-ch, so the default-low state won't exactly be compatible with the PMOS target.
Tim