Opinion on Layout Example

[mrburnzie]

Hi!
I'm looking to use TPS562200DDCR.

The example layout is quite an interesting one and I would like to get comments on it from experienced pcb designers.
What do you think about the SW node routed on the other layer as well?


Datasheet: https://www.ti.com/lit/ds/symlink/tps563200.pdf?ts=1671536497284
Page: 24

[tszaboo]

It doesn't look particularly good. I would probably move the bypass caps south of the IC, and route GND below it. I also don't understand the VFB routing. I think the layout is made for 2L boards, where the EMC considerations are not important. Look at the EVM. Those loops are gigantic, and even the inductor is oversized. Strange, because the IC isn't really old tech.

[rsjsouza]

Indeed. I would have expected the shortest path between SW and the output inductor, as mentioned even on the app note listed on the product's page (check section 3)
https://www.ti.com/lit/an/slva922/slva922.pdf

The GND under the device might not be as wide as they claim on the same document above, but being 2A that shouldn't be too hard to achieve.

[T3sl4co1l]

Better like this:

The inductor can be adjacent so the SW node has basically zero size, and the bootstrap cap is a small trace sneaking around just below.

The ground doesn't even need to flow under the chip, fine to use a couple more vias to do the same thing and then SW can go under the chip to BS without any vias on SW.

Note they recommend inner layer, i.e. this is a 4+ layer layout.  So you can have inner/bottom copper covering (surrounding) the switch node with ground pour, so it doesn't expose any emissions.  I don't mind having fair sized pours like that, as long as nothing else needs inner-1 in the area of course.  Which, you'll usually be putting this in a PSU section by itself, so that's fine, but be careful on high density builds.

Tim