Please thoroughly read AND understand the following white paper, there are many more:
https://www.nexperia.com/applications/interactive-app-notes/IAN50006_Power_MOSFETs_in_linear_mode
Unfortunately, misinformation on this subject is rampant --
Below the ZTC point, if a small region is at a higher temperature than the rest of the die, it will draw more current and dissipate more power becoming even hotter.
This is blatantly false -- but in a subtle way that is easily missed.
The NTC is
a necessary BUT NOT SUFFICIENT factor for instability.
The realization is simple. If two thermally-independent transistors are wired in parallel, operated in the NTC region, there will be some temperature difference between them -- not necessarily fatal (total power could be less than individual ratings), but also not wholly disparate, i.e. they will still share
some current, if just not all of it.
But that temperature difference depends on thermal resistance. Namely, the differential thermal resistance between devices (or, between different points on a given die).
It's perfectly possible, acceptable, and normal, to operate in the NTC region, at power levels that are low in relation to the thermal resistance within the part.
And since a die (and the copper backing) are quite conductive, it's easily possible to have a full SOA free of 2nd breakdown, in the NTC region. It's also possible to have very little SOA, where the NTC is just that strong, or thermal resistance is poorer.
Which is also why small devices simply don't have 2nd breakdown; they overheat completely, not enough temperature drop across the thing to activate the instability.
The
most correct (but still ultimately absolutely inconclusive -- but necessarily so) appnote I know of is
https://www.infineon.com/dgdl/Infineon-ApplicationNote_Linear_Mode_Operation_Safe_Operation_Diagram_MOSFETs-AN-v01_00-EN.pdf?fileId=db3a30433e30e4bf013e3646e9381200which concludes in the lamest possible way at the top of page 11: "This means that the temperature coefficient must be known. The latter cannot be easily calculated." In other words, because manufacturers don't publish mechanical construction of their devices (for obvious reasons?),
we can only know about stability by the SOA.
---
Regarding IGBTs, generally you would assume they are worse, as current density is much higher, and the minority carrier mechanism should tend to have even worse tempco. Indeed, many don't have a SOA plot
at all, and of those that do, many only give very short time scales (that might be relevant for overload conditions but not DC).
That said, I've seen more and more lately, it seems like, that show a wide SOA --
https://www.onsemi.com/pdf/datasheet/ngtb40n120fl3w-d.pdf for example.
I might not trust that SOA very much, and would want to run a spot test on a sample device before putting something into production that depends on the behavior.
Tim