Power Supply Staging for Multiple REF102 Voltage Reference

[EPAIII]

Yes, that is the TI Application Report that I have been referring to for the past several posts.

And I am talking about ONE stack of the 50xx chips in series, all powered by the ONE power supply. The ones in actual use for a given test would all share the same load current in addition to the current from the power supply. I thought that was obvious in the discussions above.

https://e2e.ti.com/blogs_/archives/b/precisionhub/posts/understanding-voltage-references-part-3-how-to-achieve-shunt-reference-flexibility-with-series-reference-precision

Its desirable to have all referrences operating at the same current to ensure even dissipation. It may be more ecconomical .
Daqq posted this previously.... http://www.ti.com/lit/an/sbaa203/sbaa203.pdf

[Kleinstein]

With the string of regulators in shunt mode the load current would reduce the current seen by the regulators, it would not add to it. So one has to set a working current for the reference and this would also limit the maximum load current. So if one sets a current of some 3 mA the regulation may work to a a load current of  maybe 1.5 mA, leading to the references than startung to show a load effect when there current drops below about 1.5 mA.
The reference actually used (in parallel to the load) would see the reduced current, the other references in the string would see there normal current.
In case of to much load the voltage would drop and the current source would see more voltage headroom - up to the full supply in case of a short over the full string.

[magic]

It all depends on polarity of load current and which end of the chain is driven by the CCS.

I recommend drawing a schematic

[EPAIII]

Oh my goodness, I had not drawn the current diagram yet, but you are absolutely right. What it amounts to is part of the power supply's current, that 3 mA minimum, will flow through the load instead of through the stack of VR chips. And if I design that minimum value of 3 mA into the circuit, then, once a load is connected (assumedly a resistive load) the current through the chips will be less than 3 mA and they may cease to maintain their rated Voltage. So I should design for a higher quiescent current, perhaps 8 or 10 mA. I need to read the spec sheet and Reference document more closely, with a actual circuit diagram at hand.

But it still seems that this is a workable concept. And since the supply current and total current will not vary, it still seems reasonable to have a simple current regulation circuit, perhaps just a series resistor to drop the extra Voltage.

I wonder if this can be properly simulated with one of the SPICE programs. Download time!

With the string of regulators in shunt mode the load current would reduce the current seen by the regulators, it would not add to it. So one has to set a working current for the reference and this would also limit the maximum load current. So if one sets a current of some 3 mA the regulation may work to a a load current of  maybe 1.5 mA, leading to the references than startung to show a load effect when there current drops below about 1.5 mA.
The reference actually used (in parallel to the load) would see the reduced current, the other references in the string would see there normal current.
In case of to much load the voltage would drop and the current source would see more voltage headroom - up to the full supply in case of a short over the full string.