getting 1s , 0.1s pulse using 10Mhz clock

[electros6]

hi guys,
            I saw an HP frequency counter which has custom ASIC for producing 1s and 0.1s pulse for gate signal. we can also do it in any CPLD or FPGA. My question is by using counter for clock dividing we get output pulse in the multiples of (2^counter value). please somebody tell me what is the schematics which was created in the CPLD or FPGA while programming to get such 1 or 0.1s pulse.

[theatrus]

An up counter with a compare and set?

[vk6zgo]

Divide by 10 is done all the time with hardware using a chain of "divide by 2" circuits in conjunction with feedback loops.(This is already done internally in many devices,but it is useful to know how to do it with basic bistables)

What you can maybe do is work out what hardware configuration is needed,draw a logic diagram,then program your device to perform that function.

[Dave]

If I catch his vibe, he wants to view the schematic of such a circuit, so he can replicate it on a breadboard or something like that.
I typed up a circuit for generating a 100 clock cycle pulse when the input is triggered. This is what the schematic looks like:


Not that useful, is it?

[miguelvp]

He can just compile this and look at the fabric too
I threw it together pretty quick so I don't even know if it will compile.

Code: [Select]

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY pulse IS
PORT(
   clk         : IN STD_LOGIC; -- 10MHz clock
   pulse_1s,
   pulse_100ms : OUT STD_LOGIC);
END pulse;

ARCHITECTURE behavior of pulse IS
SIGNAL pulse_1s, pulse_100ms : STD_LOGIC;
-- One second counter up to 10,000,000 requires 24 bits.
SIGNAL cnt_1s : STD_LOGIC_VECTOR(23 DOWNTO 0);
-- 100 ms counter up to 1,000,000 on a 10MHz clock requires 20 bits.
SIGNAL cnt_100ms : STD_LOGIC_VECTOR(19 DOWNTO 0);
CONSTANT c_1S_PULSE_LENGTH : STD_LOGIC_VECTOR(23 DOWNTO 0) := x"000064"; -- 100 clock cycles (100 microseconds at 10MHz)
CONSTANT c_100MS_PULSE_LENGTH : STD_LOGIC_VECTOR(19 DOWNTO 0) := x"00064"; --  100 clock cycles (100 microseconds at 10MHz)

PROCESS
BEGIN
   WAIT UNTIL(clk'EVENT) AND (clk = '1');


   IF(cnt_1s = 10000000) THEN
      cnt_1s <= x"000000";
   ELSE
      cnt_1s <= cnt_1s + 1;
   END IF;

   IF(cnt_100ms = 1000000) THEN
      cnt_100ms <= 0;
   ELSE
     cnt_100ms <= cnt_100ms + 1;
   END IF;

   IF(cnt_1s < (10000000-c_1S_PULSE_LENGTH)) THEN
      pulse_1s <= '0';
   ELSE
      pulse_1s <= '1';
   END IF;

   IF(cnt_100ms < (1000000-c_100MS_PULSE_LENGTH)) THEN
      pulse_100ms <= '0';
   ELSE
      pulse_100ms <= '1';
   END IF;
END PROCESS;
END behavior;

Edit: fixed hex constants, and last if statement checking the wrong counter.

[vk6zgo]

If I catch his vibe, he wants to view the schematic of such a circuit, so he can replicate it on a breadboard or something like that.
I typed up a circuit for generating a 100 clock cycle pulse when the input is triggered. This is what the schematic looks like:


Not that useful, is it?

The simplest way conceptually,would probably be to draw up one "divide by 10" circuit,then cascade as many as were needed to get the required count.

Back when I learnt this stuff,we were using 12AT7 twin triode valves for each bistable.

A Sync Pulse Generator  for a 625line BW TV system used a crystal on 31.25 kHz,so we had one "divide by two" for the line syncs,& a separate chain of division by 625 to get the field syncs.

I can't remember quite how we did it,though.
It obviously wasn't 125 "divide by 5" stages in cascade---------we could have kept the building warm from all those tubes!
I had to think about that stuff then,but have tried not to,ever since!

[vk6zgo]

I don't think he wants to do it in the most practical way.
He seems to be a bit stuck trying to get his head around the concept of dividing by other than multiples of 2.

Except that I doubt 4017s would work at 10MHz,he could use 8 of them to get the same result.

[PE1RKI]

what about using a PLL that has a 17bit programmable divider for the clock as divider?
divide 10mhz by 128 with a 4040,then use the PLL as a 78125 divider. only 2 ic's.

[dannyf]

Get mcu and divided it down.

Any sot23 or 8pdip mcu would do that.