How to multiply a clock signal

[caius]

Hi all,
I have the need to multiply a clock signal (a square wave which goes from around 200KHz to 1MHz).Specifically I need to obtain a 4x multiply factor like in the attached scope snaps.
I was thinking to use some PLL ICs (like the NB3N5xx) but it seems they can't accept on input such low frequencies.I could use a 4069 CMOS but I don't have room on PCB to implement all his circuit so a all-in-one solution (in SMD package preferibly) would be the best.Can someone give me a an idea?Thanks in advance.

[Benta]

The ON Semi FS7140/7145 might do it, but you need an I²C bus in your system.

[caius]

Thanks for the advice but I can't implement a I2C bus in my design, it's a simple reproduction of a custom IC in DIL42 package.

[Benta]

You get 8-pin MCUs for below a dollar today, so that could be your I²C control.

[caius]

Yes, I know they are cheap nowadays but it's really not worth it for a such simple design.Besides, my reproduction has to operate in a 5V system while the PLL and MCU are 3.3V.I'm looking for something simpler and immediate.

[BrianHG]

Hmmm, that's a 5 octave spread.  2x octave would have been more feasible.  Like 200k to 400k, or, 500k to 1m, but not 200k to 1m.

Do you need to keep a perfect relative phase?

Once again, as mentioned, an 8 pin MCU which has a timer input and PWM out can be an all in 1 IC solution, but you need to program it.

Unfortunately, though there are PLL ICs from TI which can to multiply a 200khz through 1mhz signal by 4, you need to select small window, say +/- 10% your center frequency you will be operating within, otherwise the oscillator will loose lock and they happen to cost more than an MCU.

[Benta]

TI CDCS504?

Edit: scratch that, minimum input is 2 MHz.

[BrianHG]

Yes, I know they are cheap nowadays but it's really not worth it for a such simple design.Besides, my reproduction has to operate in a 5V system while the PLL and MCU are 3.3V.I'm looking for something simpler and immediate.

These voltages aren't any problem to any MCU today which will operate between 1.8v and 5v, easily...

[caius]

OK, thanks for advice.I'd probably try the MUC+PLL solution although I have to program the first (I'm mainly an hardware guy with some programming skills)

[Kalvin]

For example the Microchip PIC16F15313 is available in 8-pin package for $0.46 containing 4 x Configurable Logic Controller (CLC) which could be useful as phase comparator, quite extensive PWM and NCO capabilities for frequency generation and some on-chip analog functionalities for analog phase comparison if required, which should provide good starting point.
http://www.microchip.com/wwwproducts/en/PIC16F15313
Disclaimer: I have not used this chip, I just checked what is available from Microchip.

[RoGeorge]

With XOR gates.

[joeqsmith]

With XOR gates.

Maybe 8X and a /2 to get to 50%.

I was thinking about that and it would not work (the DFF on the end).  So assuming you stretch the first stage, you would have two pulses near each other on every edge, if that makes sense.   How close would be based on the delay you add.   You really need to add some constraints to help weed out some ideas.....

Quick build on white board using 74HC.  #89 with input at 1MHz.   Slow it down, you get the idea.   

[cdev]

Interesting related application (division, timestamping) with PIC chips

http://www.leapsecond.com/pic/
http://www.leapsecond.com/pic/picpet2.htm
http://www.leapsecond.com/pic/picpet.htm
http://www.leapsecond.com/pic/picdiv.htm

[joeqsmith]

Multiply, not divide or I missed something which is very possible. 

[Ian.M]

If I had to choose a chip in the next five minutes I'd probably go for the PIC16F15323. (same family as PIC16F15313 above but with more pins and peripherals)

At f=1MHz in, its a little fast to bit-bang it.  There are two options - if you need as close as possible synchronisation to the input signal edges, you can use a CLC as an XOR + an analog comparator with a RC delay, you can get a pulse on every edge at 2f.  Square that up with Timer 2 in monostable mode, then double the frequency again with another CLC and analog comparator.

While that lot's running in hardware, the code is looping capturing the period of the input signal using a free running Timer 1 and the CCP module to timestamp every 16th rising edge, and for every capture, calculating the delta-t since the previous one and dividing it by 64 to get a new period to stuff in the monostable.   Even at 1MHz in there are 128 clock cycles to get that done in so it can probably be coded in tightly written C.

Alternatively, if you don't mind a fair bit of jitter, run a PWM with Timer 2 postscaler set to 16, and in every Timer 2 interrupt adjust the period to 1/4 of the last input signal period.   Keep track of the relative drift and bump the period rounding up or down accordingly to keep the 4x output within +/-1 cycle of 64 in 16 input cycles with no culminative error.

Both will of course fail if the input frequency is rapidly swept, but can recover within 32 input clock cycles.