Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.11.2.446 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. Tue Jul 28 13:17:54 2020 Command Line: synthesis -f adc_ms_b_adc_ms_lattice.synproj -gui -msgset /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/promote.xml Synthesis options: The -a option is MachXO. The -s option is 3. The -t option is TQFP100. The -d option is LCMXO1200C. Using package TQFP100. Using performance grade 3. ########################################################## ### Lattice Family : MachXO ### Device : LCMXO1200C ### Package : TQFP100 ### Speed : 3 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = adc_ms. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1 (searchpath added) -p /usr/local/diamond/3.11_x64/ispfpga/mj5g00/data (searchpath added) -p /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms (searchpath added) -p /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1 (searchpath added) Verilog design file = /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v Verilog design file = /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v Verilog design file = /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_tx.v NGD file = adc_ms_b_adc_ms.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v. VERI-1482 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(7): empty port in module declaration. VERI-1294 Analyzing Verilog file /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v. VERI-1482 Analyzing Verilog file /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_tx.v. VERI-1482 Analyzing Verilog file /usr/local/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo.v. VERI-1482 Top module name (Verilog): adc_ms INFO - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(3): compiling module adc_ms. VERI-1018 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(50): expression size 32 truncated to fit in target size 6. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(56): expression size 32 truncated to fit in target size 6. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(141): expression size 32 truncated to fit in target size 15. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(200): expression size 32 truncated to fit in target size 15. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(210): expression size 32 truncated to fit in target size 15. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(217): expression size 32 truncated to fit in target size 15. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(237): expression size 32 truncated to fit in target size 15. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(271): expression size 32 truncated to fit in target size 15. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(295): expression size 32 truncated to fit in target size 16. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(362): expression size 32 truncated to fit in target size 4. VERI-1209 INFO - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_tx.v(2): compiling module uart_tx. VERI-1018 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_tx.v(35): expression size 32 truncated to fit in target size 3. VERI-1209 INFO - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v(4): compiling module uart_rx. VERI-1018 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v(35): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v(53): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v(56): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v(72): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v(84): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v(87): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(37): net result_content[47] does not have a driver. VDB-1002 Loading NGL library '/usr/local/diamond/3.11_x64/ispfpga/mj5g00e/data/mj5gelib.ngl'... Loading NGL library '/usr/local/diamond/3.11_x64/ispfpga/mj5g00/data/mj5glib.ngl'... Loading NGL library '/usr/local/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'mj5g17x12.nph' in environment: /usr/local/diamond/3.11_x64/ispfpga. Package Status: Final Version 1.19. Top-level module name = adc_ms. WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(302): Register timer_gate_r[0]_458 is stuck at One. VDB-5014 WARNING - synthesis: I/O Port p1 has no net and is unused. ######## Missing driver on net result_content[47]. Patching with GND. WARNING - synthesis: Bit 0 of Register frame_content is stuck at Zero WARNING - synthesis: Bit 0 of Register uart_frame_r is stuck at Zero WARNING - synthesis: Bit 1 of Register uart_frame_r is stuck at Zero WARNING - synthesis: I/O Port p1 has no net and is unused. WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(279): Register runup_set_i0 is stuck at One. VDB-5014 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(279): Register runup_set_i11 is stuck at Zero. VDB-5013 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(370): Register uart_frame_state_i2 is stuck at Zero. VDB-5013 WARNING - synthesis: /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(370): Register frame_content__i17 is stuck at One. VDB-5014 GSR will not be inferred because no asynchronous signal was found in the netlist. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in adc_ms_drc.log. Loading NGL library '/usr/local/diamond/3.11_x64/ispfpga/mj5g00e/data/mj5gelib.ngl'... Loading NGL library '/usr/local/diamond/3.11_x64/ispfpga/mj5g00/data/mj5glib.ngl'... Loading NGL library '/usr/local/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'... WARNING - synthesis: logical net 'n6925' has no load. WARNING - synthesis: input pad net 'n6925' has no legal load. WARNING - synthesis: DRC complete with 2 warnings. All blocks are expanded and NGD expansion is successful. Writing NGD file adc_ms_b_adc_ms.ngd. ################### Begin Area Report (adc_ms)###################### Number of register bits => 257 of 1419 (18 % ) CCU2 => 45 FD1P3AX => 114 FD1P3AY => 2 FD1P3IX => 28 FD1P3JX => 5 FD1S3AX => 90 FD1S3IX => 17 FD1S3JX => 1 GSR => 1 IB => 4 L6MUX21 => 1 OB => 25 ORCALUT4 => 294 PFUMX => 19 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 4 Net : cnt_5, loads : 132 Net : uart_divider_3, loads : 65 Net : uart_divider_0, loads : 40 Net : mclk_c, loads : 24 Clock Enable Nets Number of Clock Enables: 24 Top 10 highest fanout Clock Enables: Net : uart_divider_3_enable_52, loads : 44 Net : cnt_5_enable_63, loads : 43 Net : cnt_5_enable_84, loads : 16 Net : cnt_5_enable_46, loads : 8 Net : uart_rx_a/uart_divider_0_enable_10, loads : 8 Net : uart_divider_3_enable_11, loads : 8 Net : uart_rx_a/uart_divider_0_enable_3, loads : 6 Net : uart_frame_start, loads : 5 Net : cnt_5_enable_52, loads : 4 Net : cnt_5_enable_81, loads : 4 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : uart_divider_3_enable_52, loads : 44 Net : cnt_5_enable_63, loads : 43 Net : n6691, loads : 33 Net : state_0, loads : 21 Net : uart_frame_cnt_0, loads : 21 Net : state_1, loads : 20 Net : uart_frame_cnt_2, loads : 20 Net : n9, loads : 20 Net : state_4, loads : 19 Net : uart_rx_a/uart_rx_cnt_0, loads : 17 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk3 [get_nets uart_divider[3]] | 200.000 MHz| 120.424 MHz| 4 * | | | create_clock -period 5.000000 -name | | | clk2 [get_nets mclk_c] | 200.000 MHz| 168.039 MHz| 3 * | | | create_clock -period 5.000000 -name | | | clk1 [get_nets cnt[5]] | 200.000 MHz| 53.729 MHz| 11 * | | | create_clock -period 5.000000 -name | | | clk0 [get_nets uart_divider[0]] | 200.000 MHz| 94.491 MHz| 5 * | | | -------------------------------------------------------------------------------- 4 constraints not met. Peak Memory Usage: 179.969 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 1.687 secs --------------------------------------------------------------