Setting log file to '/home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file /usr/local/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo.v
(VERI-1482) Analyzing Verilog file /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v
WARNING - /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(8,3-7,12) (VERI-1294) empty port in module declaration
(VERI-1482) Analyzing Verilog file /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v
(VERI-1482) Analyzing Verilog file /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_tx.v
INFO - /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(3,8-3,14) (VERI-1018) compiling module adc_ms
INFO - /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/adc_ms.v(3,1-390,10) (VERI-9000) elaborating module 'adc_ms'
INFO - /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_tx.v(2,1-51,10) (VERI-9000) elaborating module 'uart_tx_uniq_1'
INFO - /home/jarin/storage/main/backup_mg/contest/tah/mm/proj/fpga/1/uart_rx.v(4,1-111,10) (VERI-9000) elaborating module 'uart_rx_uniq_1'
Done: design load finished with (0) errors, and (1) warnings