Here is some fun with hierarchical sub-circuits in LTspice. I spent a lot of time procrastinating over the design of the ring counter section of the computers timing unit. One way of making a ring counter is to make a binary counter and decimal decode it. However this method is fraught with timing glitches in the decoded decimal outputs, which are completely intolerable in this application. In IC logic design this is easily dealt with by making the binary counter feeding the 1-of-n decimal decoder synchronous, but building a glitch-free 1-of-38 decoder and synchronous counter with discrete DTL gates is another matter.
Another way to make a ring counter is with a shift register that continuously circulates a single set bit. This method isn't very economical on components as a single DFF is required for each count, but it is completely immune to the problem of decoding/timing glitches. Due to the latter very important trait, this is how I have elected to build the ring counter. There are simpler ways again to build a discrete ring-counter, but I didn't want to compromise on the speed and noise immunity of my established DTL gate circuitry. The shift register method also has the shortest clock-to-Q-out propagation delay as there is no decoding to ripple through.
So, anyway, a total of 38 DFF's are to be accommodated on 8 circuit cards (currently under assembly). Here is the complete ring-counter (in addition to a minor necessary section of the associated run-time control logic of the Major State Generator) of a few thousand, individual discrete components, simulated in SPICE using sub-circuits for the duplication:
![](https://www.eevblog.com/forum/projects/homebrew-digital-computer-system/?action=dlattach;attach=127629;image)
The three DTL sub-circuits are the DFF, an inverter and an AND gate, represented in the top-level schematic by the linked/associated custom *.asy symbols:
![](https://www.eevblog.com/forum/projects/homebrew-digital-computer-system/?action=dlattach;attach=127631;image)
The simulation simply runs a complete T0 through T37 count sequence as per a Fetch machine state at the trigger of a run command pulse:
![](https://www.eevblog.com/forum/projects/homebrew-digital-computer-system/?action=dlattach;attach=127633;image)
I've been verifying the logic design of a lot of the computers circuitry this way. I just have a library of discrete component sub-circuits and build the top-level simulation schematics with standard logic symbols.