Homebrew digital computer system

[GK]

I needed a break from the endless hours of soldering components and I've run out of 1N4148's anyway (silly, I only ordered 2000), so I've gone back to the mechanical construction. To make things a little more manageable I decided to break the card frame into separate units, 3 card rows in height. Here is how far I got with the first unit this afternoon. I've only got 2 shelves attached to the side panels and no back-plane yet, but it's rock solid. The back plane will be open for air flow, made up mostly of 2 horizontal angle extrusions card per level, the full width of the frame, to which the card DIN41612 mating plugs will mount.
 
My priority now is the finish this card frame unit and get it mounted unto the actual 19" rack, along with the power supply circuitry and the control panel. Then I've be moving straight onto finishing the system clock electronics and the control circuitry for the control panel.

[GK]

Hi,

Yes, I picked that one up over a year ago on Abebooks for $1 plus postage 

[GK]

I doubt it is the instructions to build one since it is a textbook.

The PDP-8 clone is developed in a 63 page chapter called "Designing a Minicomputer" using the ASM method:

http://en.wikipedia.org/wiki/Algorithmic_State_Machine

That chapter is then followed by "Building the Minicomputer" which is only 27 pages and gives simplified logic diagrams only of a very limited number of parts and only to give clarity to the description.

It's all there but to build their actual clone design you have to transcribe the ASM to logic yourself.

[GK]

Finally have this 3-shelf section of card frame finished.





Here is the 19" rack frame that it is going to be installed into (tomorrow):

[London Lad]

I can't wait to see the looms on the back of those edge connectors :-)

[GK]

For the most part, there won't be many looms as such, but wires routed in the shortest possible path from one edge connector to another.

[baljemmett]

Finally have this 3-shelf section of card frame finished.

You're a crazy dude, GK, and I like it - much admiration!

[c4757p]

Absolutely mental in the best way possible

[London Lad]

For the most part, there won't be many looms as such, but wires routed in the shortest possible path from one edge connector to another.

Like a web of intrigue ?

[Dave Turner]

Are you going to wire-wrap the backplane? That was the classic method.

[voltz]

Following this project with interest. You must be a bit mad to do this but its brilliant!. Much respect and can't wait to see the thing running. The very best of luck there.

[GK]

The book I got was the original 1980 edition. Your's looks later because the pages you show describe the LD20 where mine is the LD15. I wonder what the differences were. Is there a description of changes in there somewhere? Preface maybe?

Mine is the second edition, dated 1987. Unfortunately the preface lists no differences in the chapters concerned with the PDP8 clone.

[GK]

Finally have this 3-shelf section of card frame finished.

You're a crazy dude, GK, and I like it - much admiration!

Are you going to wire-wrap the backplane? That was the classic method.

Following this project with interest. You must be a bit mad to do this but its brilliant!. Much respect and can't wait to see the thing running. The very best of luck there.

Lol, thanks..... I haven't progressed that much with the mechanical construction. Christmas stuff getting in the way. Have also mostly been busy etching/drilling/loading/soldering circuit cards both for this and my analog computer project - there is just endless hours of work. The backplane won't be wire-wrapped as the sockets aren't suitable. Anyway, as far as the rack goes I have the first part of the card frame installed and the control panel dummy fitted.
As I am progressing steadily with the cards I will soon be able to start wiring the backplane and get the programmable system clock, program counter register and the control logic operational to the extent that I can set the clock frequency from the control panel as well as load the program counter register from the switch register. That will still be far from an operation machine, but will be a psychologically pleasing milestone in the construction to actually see the beginnings of something (functional) come to fruition from the endless hours of soldering discrete components besides the ever increasing stack of completed circuit cards.

I am also very much looking forward to writing my first program on this machine. I think my first demo program will be a "Knight Rider" display on the accumulator register bit indicator LEDs using the left/right bit shifting commands. Eventually my main goal is to put the computer to use processing digital modes  and automating my CTM-2K 500kHz (2kW carrier power rating on AM) radio transmitter (the larger unit shown in the picture attached immediately below) on the newly established 630m radio band.

[GK]

I now have the system clock (4 cards) up and running with the clock frequency programmable from the control panel. Single-sided, un-etched PCB strips serve as power distribution buss bars between card slots. The other 4 card slots on this lowest shelf are going to be soon filled with the cards containing the remaining control panel logic and the Major State Generator. The 8 card slots of the card frame shelf immediately above will be occupied entirely by a 38-stage ring counter; a timing unit from which all operational sequences during the running of a major (machine) state are decoded/derived.

The Fetch state, for example, uses all 38 timing states (designated T0 through T37) of the ring counter. At T0, the Memory Address Register and the Instruction Register are cleared. At T1 the carry flip-flop of the Arithmetic Logic Unit is set. At T2 through T17 the 16 bits of the Program Counter Register are shifted serially into the Memory Address Register, and at the same time circulated back into the PC register via the ALU. Because the ALU full-adder carry flip-flop was set at T1, at the end of the PC>MA data transfer the value stored in the PC is incremented by 1, ready for the next fetch cycle. At T18 the carry flip-flop is cleared. At T20 through T35 the 16 data bits of the addressed memory location (the Instruction Word) is shifted into the Memory Buffer Register. At T36.5 the 3-bit Instruction register is (parallel) loaded with the three MSB's of the IW. At T37 the Defer flag flip-flop is set if the Indirect Addressing bit of the IW is set, meaning the machine will run a Defer state immediately after the Fetch sequence rather than going straight to an Execute state. That completes the T0-T37 Fetch machine state, which is run in the exact same sequence for every single instruction.

The sequence of events during the Execute state, of course, will depend on the specific instruction being executed. But anyway, the timing units is, essentially, the "spine" of the whole computers architecture, so it's my priority now (aside from wiring up the 4-card PC register on the 3rd shelf) to get those cards loaded, installed and wired.   
 
However in the meanwhile I need to buy a bunch of cable ties and P-clamps otherwise things are going to start getting really messy.............

[GK]

Here is some fun with hierarchical sub-circuits in LTspice. I spent a lot of time procrastinating over the design of the ring counter section of the computers timing unit. One way of making a ring counter is to make a binary counter and decimal decode it. However this method is fraught with timing glitches in the decoded decimal outputs, which are completely intolerable in this application. In IC logic design this is easily dealt with by making the binary counter feeding the 1-of-n decimal decoder synchronous, but building a glitch-free 1-of-38 decoder and synchronous counter with discrete DTL gates is another matter.
Another way to make a ring counter is with a shift register that continuously circulates a single set bit. This method isn't very economical on components as a single DFF is required for each count, but it is completely immune to the problem of decoding/timing glitches. Due to the latter very important trait, this is how I have elected to build the ring counter. There are simpler ways again to build a discrete ring-counter, but I didn't want to compromise on the speed and noise immunity of my established DTL gate circuitry. The shift register method also has the shortest clock-to-Q-out propagation delay as there is no decoding to ripple through.

So, anyway, a total of 38 DFF's are to be accommodated on 8 circuit cards (currently under assembly). Here is the complete ring-counter (in addition to a minor necessary section of the associated run-time control logic of the Major State Generator) of a few thousand, individual discrete components, simulated in SPICE using sub-circuits for the duplication:




The three DTL sub-circuits are the DFF, an inverter and an AND gate, represented in the top-level schematic by the linked/associated custom *.asy symbols:




The simulation simply runs a complete T0 through T37 count sequence as per a Fetch machine state at the trigger of a run command pulse:




I've been verifying the logic design of a lot of the computers circuitry this way. I just have a library of discrete component sub-circuits and build the top-level simulation schematics with standard logic symbols.     

[SeanB]

I would also suggest getting some multicore phone cable and stripping it for the coloured pairs inside. That way you can organise cables according to function, though you will have a lot of white and red wires extra for some use.

[GK]

Well, I have a bunch of CAT5 cable that I am stripping. That has four pairs of different colours - green/green-white, blue/blue-white, orange/orange-white and brown/brown-white.

[ale500]

I come hier back every few weeks hoping to see some new info... I hope you didn't give up ! 

[GK]

I come hier back every few weeks hoping to see some new info... I hope you didn't give up ! 

On no, definitely not  I just have many other projects on the go. As a matter of fact I just etched a few more boards for this project last week. Haven't had a chance to start loading them yet. I almost have all of the computers control panel and associated logic completed and operational.

[joeqsmith]

I like it! 

[technix]

Seems really impressive, although if I were you I would use a whole bunch of CPLDs double side loaded to reduce board size and cost. Programming them and JTAG through them will be tedious though.

[GK]

Well, I could just program any one of a number of modern microcontrollers with some minor additional support hardware to hook up to my control panel, to emulate a PDP, but that would be besides the point.
 

[stevenhoneyman]

Seems really impressive, although if I were you I would use a whole bunch of CPLDs double side loaded to reduce board size and cost. Programming them and JTAG through them will be tedious though.

hahaha