I'd like to use 10:1 10M probes with my Tek 7904 500MHz oscilloscope whose wide-bandwidth vertical plugins sport 50-ohm inputs. I've elected to build a 4-channel buffer amplifier for this purpose. I'm aiming for a bandwidth of at least 250 MHz. While this is only half the bandwidth of the 7904 mainframe I feel that there is no point going any more exotic as the achievable bandwidth with 10:1 10M probes limited. After a couple of hours of head scratching this evening here is my preliminary schematic.
The unit to be constructed will have four identical channels. A channel is comprised of a 1M input termination, AC/DC coupling capacitor/switch(relay) and input protection followed by an RF JFET buffer, followed by a x2 Av op-amp based amplifier with a 50-ohm output Z for driving the scope input via a length of connecting coax.
The ADA4899-1 output will clip/limit at about 3V peak driving the combined 100 ohm load + 300 ohm feedback resistance. This gives a full scale input of 15V peak with a 10:1 probe, though in use an upper limit of 10V peak would be considered the useful maximum. I feel that this is more than adequate as high frequency solid-state circuits seldom have ac amplitudes greater than 20Vpp.
One thing that has to be accounted for is the positive DC offset present due to the gate-source voltage of the JFET. I've elected to use a small 8-bit PIC uC (only 7 IO pins required) in combination with a four-channel 12-bit serial DAC to auto-null each channel immediately after power-on.
At first I considered using a uC with an internal ADC and MUX to measure the DC-level output of each channel during the auto-null, but that would require level-shifting to accommodate the ADCs input range, and that would have a significant degree of inaccuracy necessitating manual trimming for each channel. So as an alternative I decided to use an external MUX controlled by the uC feeding a zero-crossing comparator rather than an ADC.
The uC will be programmed with a simple successive approximation routine - each DC-null will take twelve bit-toggles with the final status for each bit determined by the output of the comparator. The end result of this is that the DC offset will be auto corrected to a couple of mV (which is more than adequate) without the need for any manual tweaking or precision components. During nulling the uC activates relay K2 to short the JFET input to ground.
I can't see anything immediately bothersome or not straight forward, though I have yet to select an suitable RF JFET. Require something with a min. Idss on the order of 10mA; currently considering the MMBFJ309 as I notice this is what Rigol use in the DS2027A, though I'd prefer something with a smaller worse-case Vgs.
Comments?
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