High Voltage Breakdown - Conducted Noise

[23f23fwefsdf]

Background

I am working on a test setup to lifetime test high voltage insulation products.  The HV source https://www.matsusada.com/product/electrostatic-chuck-power-supplies/rack-mount/ec/ can supply +/-10kV at 20mA constant current.  The output capacitance, including DUT and cabling, is a couple hundred pF.

There are three primary functions for the test cards:
- Measure output voltage at 25kHz per channel with minimal loading
- Provide switching for 8 channels
- 1Hz measurement of leakage current

There is a controller board with an isolated UART interface.  The controller interfaces with the A/D converters through SPI over LVDS and, physically, shielded CAT5 cabling is used.  The shield is connected to the isolated ground.

The power supplies are not isolated - their return has to connect to the transimpedance amplifier ground.  The output of the voltage amplifiers is routed through the middle of the board, between the relays for creepage/clearance reasons.  It's between two ground pours that have via stitching on the edges.  The LVDS and A/D section will be shielded and the shield connected to the local ground. 

Question:

Anecdotally, when using off-the-shelf picoamp meters https://rbdinstruments.com/products/picoammeter.html (isolated), the USB communication is interrupted when there are discharge events.  In this product, the transimpedance amplifier and A/D converter are digitally isolated so the unit can float to 5kV.

How can I improve the design in this regard?  Is the current approach susceptible to conducted noise from discharge events?

Attached are the relevant schematic and layout/stackup pictures. 

[David Hess]

Is 10 kilovolts being routed through or on the printed circuit board?

Even at the level of a couple thousand volts, I have seen a variety of printed circuit board failures, but usually associated with surface contamination.

At high voltages, discontinuities in the dielectric can cause locally higher voltage gradients causing ionization in air bubbles or gaps which gradually erode the dielectric and eventually cause a short.  Reliable designs either use special materials or air wiring with a minimum of trace length on printed circuit boards.  Vacuum potting is used to prevent air bubbles.

I would put another isolation resistor directly in series with the inverting input of the transimpedance amplifiers to separate the AC and DC feedback as shown in figure 12 of National Semiconductor application note 242 attached below.

Anecdotally, when using off-the-shelf picoamp meters https://rbdinstruments.com/products/picoammeter.html (isolated), the USB communication is interrupted when there are discharge events.  In this product, the transimpedance amplifier and A/D converter are digitally isolated so the unit can float to 5kV.

I have seen that happen before even in careful designs.  I think what happens is that the ESD protection shunts the ESD to ground but the ground impedance is too high, allowing a greater than logic level pulse through the ground to produce unintended operation.

The solution I have used to prevent it is to make sure that the ESD clamp ground return is isolated from other grounds and returns the current directly to the ESD source, typically the chassis connection, with a minimum of loop area to minimize inductance.  This also means placing the ESD clamp circuit as close to the ingress point as possible.

[ace1903]

My suggestion is to put opto isolation before LVDS transmission.

[geggi1]

You should look into the way PD (Partial discharge) measurements are done on HV equipment.
https://www.hvtechnologies.com/the-basics-of-partial-discharge-testing/

[PartialDischarge]

I don't understand very well what is the goal here, seems you are trying to reinvent the wheel. Usually there are 2 types of tests for equipment with isolation running at HV:

1) Dielectric insulation test, either at DC or AC, which is carried at a margin over the maximum nominal working voltage to check the insulation. This is usually a 1s to 1min test. Successful test is a lack of arcing.
2) Partial discharge test, at the maximum working voltage to test for partial discharges with may affect the insulation over a long period of time, for equipment that is installed long term.
Partial discharges are high frequency but may occur at a low rate, and what is measured is the charge. There are special equipments to measure this. Successful test is charge less than a predetermined value (for example 10pC for intrument transformers)

[guenthert]

Background

I am working on a test setup to lifetime test high voltage insulation products.  The HV source https://www.matsusada.com/product/electrostatic-chuck-power-supplies/rack-mount/ec/ can supply +/-10kV at 20mA constant current. 

[..]

Ouch.  I wouldn't think that such high a current would be needed to verify insulation and 20mA is going to hurt in case something goes wrong.

[23f23fwefsdf]

I don't understand very well what is the goal here, seems you are trying to reinvent the wheel. Usually there are 2 types of tests for equipment with isolation running at HV:

1) Dielectric insulation test, either at DC or AC, which is carried at a margin over the maximum nominal working voltage to check the insulation. This is usually a 1s to 1min test. Successful test is a lack of arcing.
2) Partial discharge test, at the maximum working voltage to test for partial discharges with may affect the insulation over a long period of time, for equipment that is installed long term.
Partial discharges are high frequency but may occur at a low rate, and what is measured is the charge. There are special equipments to measure this. Successful test is charge less than a predetermined value (for example 10pC for intrument transformers)

This is not an *insulation test (hipot or PD) - it is a HALT test.  In this case, an oxide barrier is stressed at elevated temperature and voltage and a lifetime model is constructed.  At the product level, the parts are IR and PD tested - 60s is not a substitute for years at HV.  Also, 10pC seems to be a historical precedent and not a replacement for lifetime testing.  The noise floor for most PD equipment is ~1pC so 10pC is chosen as a reasonable threshold to detect discharges.  Some parts I have tested have 10pC inception voltages under the operational voltage, but still survive because the cycle count is low. 

PD is an AC effect, only happening when voltage changes due to capacitive charging.  In this case, the failure is due to application of electric field under DC and at high temperature (defect generation, charge trapping, thermomechanical stresses, etc).  Insulation resistance can change over the lifetime of a device.  The barrier formation process itself is also defect prone.

My suggestion is to put opto isolation before LVDS transmission.

There will be isolation on the other side of the LVDS, the LVDS transceivers and ADC shielded.

Background

I am working on a test setup to lifetime test high voltage insulation products.  The HV source https://www.matsusada.com/product/electrostatic-chuck-power-supplies/rack-mount/ec/ can supply +/-10kV at 20mA constant current. 

[..]

Ouch.  I wouldn't think that such high a current would be needed to verify insulation and 20mA is going to hurt in case something goes wrong.

Each channel is current limited to 2.5mA.  The supply can push 20mA at 10kV.  The current limiting resistor is already large, if I increase it more, the resistor divider will load the circuit. 

Is 10 kilovolts being routed through or on the printed circuit board?

Even at the level of a couple thousand volts, I have seen a variety of printed circuit board failures, but usually associated with surface contamination.

At high voltages, discontinuities in the dielectric can cause locally higher voltage gradients causing ionization in air bubbles or gaps which gradually erode the dielectric and eventually cause a short.  Reliable designs either use special materials or air wiring with a minimum of trace length on printed circuit boards.  Vacuum potting is used to prevent air bubbles.

I would put another isolation resistor directly in series with the inverting input of the transimpedance amplifiers to separate the AC and DC feedback as shown in figure 12 of National Semiconductor application note 242 attached below.

Anecdotally, when using off-the-shelf picoamp meters https://rbdinstruments.com/products/picoammeter.html (isolated), the USB communication is interrupted when there are discharge events.  In this product, the transimpedance amplifier and A/D converter are digitally isolated so the unit can float to 5kV.

I have seen that happen before even in careful designs.  I think what happens is that the ESD protection shunts the ESD to ground but the ground impedance is too high, allowing a greater than logic level pulse through the ground to produce unintended operation.

The solution I have used to prevent it is to make sure that the ESD clamp ground return is isolated from other grounds and returns the current directly to the ESD source, typically the chassis connection, with a minimum of loop area to minimize inductance.  This also means placing the ESD clamp circuit as close to the ingress point as possible.

Other insulation resistance testers that I have opened have MOVs + PTC/polyfuse in series with the input, along with some fast acting diodes to clamp.  In this case, the diodes and MOVs are connected towards the guard.  I guess the guard then has to be low enough impedance to shunt the current away from the input.  Since there is a guard, leakage over the protection devices is low.

[PartialDischarge]

This is not an *insulation test (hipot or PD) - it is a HALT test.  In this case, an oxide barrier is stressed at elevated temperature and voltage and a lifetime model is constructed.  At the product level, the parts are IR and PD tested - 60s is not a substitute for years at HV.  Also, 10pC seems to be a historical precedent and not a replacement for lifetime testing.  The noise floor for most PD equipment is ~1pC so 10pC is chosen as a reasonable threshold to detect discharges.  Some parts I have tested have 10pC inception voltages under the operational voltage, but still survive because the cycle count is low. 

PD is an AC effect, only happening when voltage changes due to capacitive charging.  In this case, the failure is due to application of electric field under DC and at high temperature (defect generation, charge trapping, thermomechanical stresses, etc).  Insulation resistance can change over the lifetime of a device.  The barrier formation process itself is also defect prone.

Understood, but I disagree with a couple of things:

1) The dielectric test even for 60s is carried at a much higher voltage than nominal, thus if coupled with an appropriate dielectric and protections for the pollution of the environment, the test results will provide a safe, non-arcing system. For example an instrument transformer for 12kV is tested at 28kVrms dielectric insulation.

2) PD is also for DC, this are covered even in IEC 60270 and is a thing for example in coaxial cables and DC link capacitors. This is where "supposedly" the long term effects are extracted with a short test so you don't have to resort for long time testing of each sample which is not practical.