High side Vgs oscillating back to 0V in miller region

[uer166]

Trying to design a 3-phase BLDC motor controller. Tinkering in simulations with one half-bridge switching leg, it seems that the high side Vgs, during turn on, turns on, blows past the "normal" miller region that I would expect to see, and then goes to -8V, and recovers with some oscillation. I'd like to see a textbook, flat miller region in this design, and I'm not sure what is causing this.

I thought about:

• The reverse recovery time of low-side body diode causes large current to shoot-through, somehow reducing high-side  FET's Vgs?
• dV/dt induced turn on of lower FET? But during the high dV/dt region, the lower FET's Vgs also goes negative

I'm not sure if either of those effects can explain the issue. I've tried adding anti-parallel diodes to gate resistors for harder turn-off. Tried slowing switching times via larger gate resistors, adding a snubber, using both logic-level and standard level FETs. Fundamentally though, I want to understand what's happening and not make it work with  trial-and-error. The current out of the half-bridge into inductor is about 20A in the simulation. Switching frequency is 25KHz, although that wouldn't matter for the edges.

[uer166]

On the Nth look, looks like a hard low-side body diode recovery is causing the oscillation. But still no idea what would fix this, apart from a FET with softer recovery.

[mvs]

On the Nth look, looks like a hard low-side body diode recovery is causing the oscillation. But still no idea what would fix this, apart from a FET with softer recovery.

No, its bounce from inductor L2. As long as low side switch U2 is conducting, there is current flowing throught L2 (V5 - U2 - GND - U1 - L2 - V5). If you close U2, SW node gets bounced. Since high side MOSFET U3 has some gate-drain capacitance this bounce influence gate-source voltage.
You can leave U3 closed and it should not change anything.

[uer166]

I don't think so, V5 isn't supplying any current, 20A is flowing *into* V5, not out of it. It's there to simulate BEMF of a motor. In the scope trace, the captured moment is when:

• U2 turns off
• Some dead-time: current flowing though U2's body out of GND into V5 and the inductor
• U3 turns on
• High current spike into U2 from U3's turn on, because body diode needs to recover
• U2's body diode recovers hard, (100A->0A in single-digit ns)
• Such fast dI/dt does weird things

....Or at least that's my theory, unless I'm woefully misunderstanding it.

Can you explain what makes you think it's L2's fault? L2 is a very very large inductor simulating motor winding that can't really cause such high frequency oscillation I think.

edit: wrong refdes..

[mvs]

Can you explain what makes you think it's L2's fault? L2 is a very very large inductor simulating motor winding that can't really cause such high frequency oscillation I think.

Voltage at SW node gets higher then you supply voltage, so there might be some inductance in play. It might be not L2, but some parasitic inductance.

I have tried to simulate your circuit in LTSpice now, and have found no issues. It works just fine. The only difference was another MOSFET type.
Where you have this BUK7Y1R7 model from? It may include some lead inductance, that another models do not have.

[uer166]

Where you have this BUK7Y1R7 model from? It may include some lead inductance, that another models do not have.

Straight from Nexperia's website. Looking at it, it's a whole subcircuit model which includes lead inductances on all pins and the lead resistance too. I think that would make the simulation even more accurate though, and maybe the issue would actually exist in real life due to parasitics.

[T3sl4co1l]

Note that lead inductance is included in the models (I assume -- you didn't show the models, so I guess they're going to be the ones from the mfg?), and you're seeing transients due to that.

Note that C1 is redundant, unless you've specified different ESR/L for each, which isn't indicated so I'm going to assume they are pure C.  (A poor assumption in LTSpice, which likes to put default parasitics on components for you.)

And yeah, you've got a 100ns dead time, which turns on the body diode, which then undergoes recovery.  SPICE is notoriously bad at recovery, but this model seems reasonably okay.

If you can handle tighter timing with the controller/driver you'll be using, consider setting dead time on the rising edge to nearly interference (say -20/0 or even -10/10 ns).  Add some series inductance (besides the package inductance) to set commutation dI/dt.  (Absorb the inductor's energy in an RC, or use an R||L, or a Vpeak clamp snubber.)  Consider adding C (or a lower R and larger C R+C) to set dV/dt at nominal load current to help prevent diode forward bias.

Alternately, use an R || D gate resistor for the low side, to delay turn-off to the same end.

If the load current is bidirectional, ideally you'd have adaptive dead time and/or drive strength (depending on load current magnitude and direction), but the next best is fixed timing with short dead time, or interference, on both edges.

Tim

[uer166]

Note that C1 is redundant, unless you've specified different ESR/L for each, which isn't indicated so I'm going to assume they are pure C.  (A poor assumption in LTSpice, which likes to put default parasitics on components for you.)

Check again, one is 1 m(illi)F, other is m(icro)F, and yes their ESRs are very different. (I admit they look the same from far away).

If you can handle tighter timing with the controller/driver you'll be using, consider setting dead time on the rising edge to nearly interference

Ah! I had this idea, this makes it so the diode is never conducting, so we can completely avoid recovery, correct? This seems a bit sketchy, wouldn't propagation delays and rise time variability in gate drivers make this hard without causing major shoot-through?

Add some series inductance (besides the package inductance) to set commutation dI/dt.  (Absorb the inductor's energy in an RC, or use an R||L, or a Vpeak clamp snubber.)

Yeah good idea, but this depends heavily on layout, I presume something like 1-5 nH is approximately correct for good plane layout?

If the load current is bidirectional

I guess it has to be for regen braking 


Thanks for great advice!! 

[T3sl4co1l]

Check again, one is 1 m(illi)F, other is m(icro)F, and yes their ESRs are very different. (I admit they look the same from far away).

If there's no parasitic as I initially assumed, they're perfectly in parallel, and SPICE doesn't care.  (SPICE also doesn't care about caps in parallel with voltage sources, but you've shown a supply inductor so that's fine!)

Since they are different, can you please show them?  Pet peeve about LTSpice.

Ah! I had this idea, this makes it so the diode is never conducting, so we can completely avoid recovery, correct? This seems a bit sketchy, wouldn't propagation delays and rise time variability in gate drivers make this hard without causing major shoot-through?

Hence the supply (switching loop) inductance to set the dI/dt of shoot-thru.

It is indeed sketchy for some controllers and drivers.  To get that precise, you might have to trim for manufacture as well as temperature, which would be ridiculous.  Most are better than their worst case figures, and you might expect some production fallout (higher than expected power dissipation) from the outliers; otherwise, for proper design you would have to simply find tighter parts (or do it yourself, maybe with a small FPGA).

It's unfortunate that there's no pressure to make better controllers.  It's not very practical to make a multi-MHz controller; all you find is regulators (integrated switch) up there.  (And still they don't set dead time correctly -- some regulators generate sub-nanosecond pulses from utterly avoidable diode recovery!)  With GaN picking up, hopefully this will start to change...

Yeah good idea, but this depends heavily on layout, I presume something like 1-5 nH is approximately correct for good plane layout?

Those transistors are a few nH themselves, and you can place them adjacent with C1 as well, getting a total of maybe 8nH.  Extra (if needed) can then be added as a lumped element, and snubbed in the same location (note that the snubber's ESL takes over in terms of setting total loop inductance).

Assuming an inner ground plane.

Tim

[uer166]

Not sure how to make it visible on schematic, but :

• C2: 1000uF, 100mOhm ESR
• C1: 1uF, 5mOhm ESR

[uer166]

Some changes/results!
Changes:

• Added parasitic inductance in switch path
• Added peak voltage snubber
• On low side made gate discharge 5 Ohms with diode
• Set dead-time of low-high transition to -10ns (0ns would still turn on body diode freewheel, -10ns seems just about right!)

There is still no clean miller plateau unfortunately  , but high side gate doesn't go as crazy as before. The high-low deadtime is set to 90ns, and there's some interesting oscillations there still (~56Mhz), see last screenshot.

Edit: some good things came out of it though, like peak shoot-through current is only 16A, while it used to be 60A because of reverse recovery and lack of the parasitic inductors.

[T3sl4co1l]

Your Miller is here:

It looks weird because the system isn't as, well, linear as you are used to.

If you mentally fill in the valley with equal flux (area under the curve) from the peak, that's where the plateau is.  The voltage overshoots partly due to inductance (you're seeing Vgs + d(Id)/dt * Ls, more or less) and partly because Vgs really is overshooting, because of course it is, it's drawing peak current in that instant.

Where I've drawn the line is, ehh, it's probably a bit higher than the actual equivalent plateau, but around there.

Tim

[uer166]

Ah I see. So I mean, the actual real question I have is whether there's anything wrong with it doing that in real design. As far as I can see all the abs. max ratings of FETs are respected, and nothing too crazy. So it "should" work just fine. The inverter hits 98.5% efficiency in sim, slightly over target (but will be brought down by shunt resistors) 

[duak]

One of my colleagues designed a similar circuit and found that he needed to add some gate to source capacitance to reduce the contribution from the Miller effect to reduce an EMI problem.   It's not shown on the datasheet, but the transconductance of this device must be very high.  Intuitively, any anomalous voltage coupled to the gates could cause trouble.  I would reduce the series gate drive resistor to 10R and start with a couple more nF between the gate and source and see what happens.

Is anyone here familiar with emitter follower circuits and their counterintuitive ability to oscillate with capacitive loads?  I wonder if a similar effect also manifests here with the upper device being a source follower?  I've done very little with Spice simulations.  I think it might be instructive to do a small signal simulation of parts of this circuit to see if there are any VHF instabilities.

Best o' luck,

[T3sl4co1l]

One of my colleagues designed a similar circuit and found that he needed to add some gate to source capacitance to reduce the contribution from the Miller effect to reduce an EMI problem.   It's not shown on the datasheet, but the transconductance of this device must be very high.  Intuitively, any anomalous voltage coupled to the gates could cause trouble.  I would reduce the series gate drive resistor to 10R and start with a couple more nF between the gate and source and see what happens.

Is anyone here familiar with emitter follower circuits and their counterintuitive ability to oscillate with capacitive loads?  I wonder if a similar effect also manifests here with the upper device being a source follower?  I've done very little with Spice simulations.  I think it might be instructive to do a small signal simulation of parts of this circuit to see if there are any VHF instabilities.

If you talk about adding capacitance from gate to source, you have to take into account the fact that you aren't connecting to the gate and source internally as such -- that is, you have package parasitics inbetween, and these can be enough to oscillate, in a similar way to the above consideration.

In general, any low impedance attached to the gate needs to be considered; transmission line stubs included, which is why we normally put the gate resistor near the transistor, to raise the minimum impedance (at any frequency) that is seen by the gate.

Tim