High impedance buffer

[BradC]

G'day all,

Going to build a unity gain high impedance buffer to follow a KVD. I've chosen the LTC1052 followed by an LT1010. This is nothing clever, and will be powered by a pair of 9V batteries driving a linear 15V regulator with the op-amp and buffer single supply. I chose the LTC1052 with external capacitors as it looked like a relatively noise & low bias chopper amp and the others I looked at had at least an order of magnitude more input bias. I already have the parts, so unless there is a wildly better option I'd like to stick with those.

As the amp has a several pA input bias, I've chosen a pair of 2N4117A Jfets configured as diodes to clamp the input as they reputedly have a leakage in the low pA. They are TO204 cans with a separate pin for the shell, so I've connected that to the guard which is driven by the output. Those JFETs are *expensive*.

I have tried where possible to match the inputs with potentially useless resistors and capacitors to match the thermal EMF and the only joints not currently accounted for are on the jfets. Unsure what to do about that.

I've laid out a single sided board to suit, but I thought I'd solicit feedback on the schematic before getting serious about the layout.

Comments welcome. (edit, yeah, yeah I know the jfets are backwards).

[Kleinstein]

The capacitor C3 is calling for trouble. A low pass filtering in the feedback path is usually a bad idea and tends to promote oscillations.

If the FETs are too expensive one could consider low leakage diodes like BAV199. The typical leakage current is comparable, but not guarantied (tested). Changes are very good to be way lower than the OPs bias.

As the LTC1052 also has diodes inside, one could consider using 2 diodes in series each and used bootstrapping, so that the extra diodes would contribute essentially no extra current as they would be a essentially 0 voltage. The extra diodes would be a coarse stage and with there capacitance would also provide some filtering.

For the output resistor one could consider have the DC feedback from behind resistors and only higher frequency feedback from before the resistor. This would be the normal circuit to isolate capacitive loads.

[BradC]

The capacitor C3 is calling for trouble. A low pass filtering in the feedback path is usually a bad idea and tends to promote oscillations.

Actually, I took that from both the LT1010 data sheet and Linear AN86 which shows that specific feedback configuration was used in the configuration I plan on using. (clip attached)
As this is only a buffer to follow a KVD I figure slower is better. I can tweak it if I see oscillations, but I figured as it was in the data sheet I could play with the values as required to tune it if it turns out to be a problem.

If the FETs are too expensive one could consider low leakage diodes like BAV199. The typical leakage current is comparable, but not guarantied (tested). Changes are very good to be way lower than the OPs bias.

They are expensive, but as I already have them (plus a spare set) I figure I'll go with that for the first incarnation. I assume like everything I'll build a few of these as I discover bits that don't behave the way I want them to behave. I've found an smd equivalent of the 4117 with essentially the same leakage characteristics, and they are 60c a pop. I was more interested in seeing how low I could get the input bias. Most choppers I looked at started with a typical value in the 10s of pA. The 1052 is typically 1pA with a max of where they other choppers start (~30pA), so I wanted to try and get an input protection configuration that wouldn't significantly eat into that. Burr Brown app note AB-064 indicates the 2N4117A can be below 200fA for the sorts of voltages dealt with here, so they shouldn't seriously degrade the chain.

As the LTC1052 also has diodes inside, one could consider using 2 diodes in series each and used bootstrapping, so that the extra diodes would contribute essentially no extra current as they would be a essentially 0 voltage. The extra diodes would be a coarse stage and with there capacitance would also provide some filtering.

I figured there would be input clamps but as I couldn't find any details on the data sheet I went with the external clamp. These are good for up to 50mA and I plan on limiting the input impedance down to a tenth of that (~3k). Now admittedly the external clamp is likely to exceed Vin by 0.6V and the absolute maximum spec is Vin+0.3v I might still do some damage, but I was hoping the input resistors would keep that under control. The fets are there to protect against my kids knocking something on the bench and stuffing 30V into the input.

For the output resistor one could consider have the DC feedback from behind resistors and only higher frequency feedback from before the resistor. This would be the normal circuit to isolate capacitive loads.

The output resistor was put in place to keep the short circuit current down. I'm not worried about damaging the LT1010. That can manage 100mA. It's there to keep the total dissipation between the linear regulator and LT1010 under control only. I'm not so worried about capacitive loads right now. Of course I might build it and find I have to be, and that'll require me having another crack at it.

Thanks for taking a look at it.

[BradC]

The capacitor C3 is calling for trouble. A low pass filtering in the feedback path is usually a bad idea and tends to promote oscillations.

Actually, I took that from both the LT1010 data sheet and Linear AN86 which shows that specific feedback configuration was used in the configuration I plan on using. (clip attached)
As this is only a buffer to follow a KVD I figure slower is better. I can tweak it if I see oscillations, but I figured as it was in the data sheet I could play with the values as required to tune it if it turns out to be a problem.

(edit) Huh, having composed this an attached the clip I now see why my configuration is incorrect. Thanks!

If the FETs are too expensive one could consider low leakage diodes like BAV199. The typical leakage current is comparable, but not guarantied (tested). Changes are very good to be way lower than the OPs bias.

They are expensive, but as I already have them (plus a spare set) I figure I'll go with that for the first incarnation. I assume like everything I'll build a few of these as I discover bits that don't behave the way I want them to behave. I've found an smd equivalent of the 4117 with essentially the same leakage characteristics, and they are 60c a pop. I was more interested in seeing how low I could get the input bias. Most choppers I looked at started with a typical value in the 10s of pA. The 1052 is typically 1pA with a max of where they other choppers start (~30pA), so I wanted to try and get an input protection configuration that wouldn't significantly eat into that. Burr Brown app note AB-064 indicates the 2N4117A can be below 200fA for the sorts of voltages dealt with here, so they shouldn't seriously degrade the chain.

As the LTC1052 also has diodes inside, one could consider using 2 diodes in series each and used bootstrapping, so that the extra diodes would contribute essentially no extra current as they would be a essentially 0 voltage. The extra diodes would be a coarse stage and with there capacitance would also provide some filtering.

I figured there would be input clamps but as I couldn't find any details on the data sheet I went with the external clamp. These are good for up to 50mA and I plan on limiting the input impedance down to a tenth of that (~3k). Now admittedly the external clamp is likely to exceed Vin by 0.6V and the absolute maximum spec is Vin+0.3v I might still do some damage, but I was hoping the input resistors would keep that under control. The fets are there to protect against my kids knocking something on the bench and stuffing 30V into the input.

For the output resistor one could consider have the DC feedback from behind resistors and only higher frequency feedback from before the resistor. This would be the normal circuit to isolate capacitive loads.

The output resistor was put in place to keep the short circuit current down. I'm not worried about damaging the LT1010. That can manage 100mA. It's there to keep the total dissipation between the linear regulator and LT1010 under control only. I'm not so worried about capacitive loads right now. Of course I might build it and find I have to be, and that'll require me having another crack at it.

Thanks for taking a look at it.

[Cerebus]

Are you sure that the 4th pin on those 2N4117As is just the case, often the 4th pin on FETs is also substrate. Could ruin your day actively driving the substrate. Neither of the 2N4117 data sheets I have is explicit on the point, if I were you I'd want to get this confirmed or denied.

[BradC]

Are you sure that the 4th pin on those 2N4117As is just the case, often the 4th pin on FETs is also substrate. Could ruin your day actively driving the substrate. Neither of the 2N4117 data sheets I have is explicit on the point, if I were you I'd want to get this confirmed or denied.

I might want to test that then. The interfet data sheet linked from the Mouser page I bought them from states "1-Source, 2-Drain, 3-Gate, 4- Case".
Never having looked at a JFet before and having 4 here on the desk, what would be a realistic way of measuring that without setting fire to a $15 FET?

[Cerebus]

Are you sure that the 4th pin on those 2N4117As is just the case, often the 4th pin on FETs is also substrate. Could ruin your day actively driving the substrate. Neither of the 2N4117 data sheets I have is explicit on the point, if I were you I'd want to get this confirmed or denied.

I might want to test that then. The interfet data sheet linked from the Mouser page I bought them from states "1-Source, 2-Drain, 3-Gate, 4- Case".
Never having looked at a JFet before and having 4 here on the desk, what would be a realistic way of measuring that without setting fire to a $15 FET?

Big resistor, say 1M, connect it to the suspected substrate. Ground the source, raise the suspected substrate (via the resistor, natch) to ~0.6V above ground and measure the current flow. If there is any, it's substrate, if there isn't it's just the case. On a 2N4117 it won't take much current to fry things, so don't omit that resistor.

[BradC]

Are you sure that the 4th pin on those 2N4117As is just the case, often the 4th pin on FETs is also substrate. Could ruin your day actively driving the substrate. Neither of the 2N4117 data sheets I have is explicit on the point, if I were you I'd want to get this confirmed or denied.

I might want to test that then. The interfet data sheet linked from the Mouser page I bought them from states "1-Source, 2-Drain, 3-Gate, 4- Case".
Never having looked at a JFet before and having 4 here on the desk, what would be a realistic way of measuring that without setting fire to a $15 FET?

Big resistor, say 1M, connect it to the suspected substrate. Ground the source, raise the suspected substrate (via the resistor, natch) to ~0.6V above ground and measure the current flow. If there is any, it's substrate, if there isn't it's just the case. On a 2N4117 it won't take much current to fry things, so don't omit that resistor.

Much appreciated. Used a 1M resistor. Pin 4 is connected to the case but there was absolutely no current between pin 4 and source. I double checked to make sure it was all good by swapping from the case to the gate, and got the expected Gate->Source current.

[guenthert]

The capacitor C3 is calling for trouble. A low pass filtering in the feedback path is usually a bad idea and tends to promote oscillations.

Actually, I took that from both the LT1010 data sheet and Linear AN86 which shows that specific feedback configuration was used in the configuration I plan on using. (clip attached)
As this is only a buffer to follow a KVD I figure slower is better. I can tweak it if I see oscillations, but I figured as it was in the data sheet I could play with the values as required to tune it if it turns out to be a problem.

No, it doesn't.  In the clip the cap provides a low impedance path for high frequencies (high pass), you implemented a low pass.

The output resistor was put in place to keep the short circuit current down. I'm not worried about damaging the LT1010. That can manage 100mA. It's there to keep the total dissipation between the linear regulator and LT1010 under control only. I'm not so worried about capacitive loads right now. Of course I might build it and find I have to be, and that'll require me having another crack at it.

Thanks for taking a look at it.

Uhm, it's a bit odd to put an output resistor after the feedback loop of the buffer.  To me that seems unnecessarily limiting the 'stiffness' and hence precision of the device.  Makes one wonder why using a buffer in the first place.  Put the resistor before and it will limit the max. current draw just the same, but w/o increasing the output resistance of the circuit.

Simulations have their limits, but these issues can be easily found using e.g. LTSpice.

[BradC]

No, it doesn't.  In the clip the cap provides a low impedance path for high frequencies (high pass), you implemented a low pass.

You are of course correct. I spotted what I'd done wrong and attempted to put an edit in my post but managed to completely munge it up and turn it into a mis-quoted reply to nobody :

(edit) Huh, having composed this an attached the clip I now see why my configuration is incorrect. Thanks!

The output resistor was put in place to keep the short circuit current down. I'm not worried about damaging the LT1010. That can manage 100mA. It's there to keep the total dissipation between the linear regulator and LT1010 under control only. I'm not so worried about capacitive loads right now. Of course I might build it and find I have to be, and that'll require me having another crack at it.

Uhm, it's a bit odd to put an output resistor after the feedback loop of the buffer.  To me that seems unnecessarily limiting the 'stiffness' and hence precision of the device.  Makes one wonder why using a buffer in the first place.  Put the resistor before and it will limit the max. current draw just the same, but w/o increasing the output resistance of the circuit.

Simulations have their limits, but these issues can be easily found using e.g. LTSpice.

To be honest I've never used a simulator in my life. I generally "simulate" in solder, but you are right. With an expected load of 10M, any worthwhile series resistance will contribute significantly to a droopy output.

This is the first time I've ever posted a design for critique before committing to solder. Glad I did

[Echo88]

Wanted to build a buffer for my KVD also a year ago, but didnt continue the project, since i got a calibrator.
Anyway, i made an Excel-file to compare different Autozero-OPs for this project. Maybe its useful to someone.

[BradC]

Wanted to build a buffer for my KVD also a year ago, but didnt continue the project, since i got a calibrator.
Anyway, i made an Excel-file to compare different Autozero-OPs for this project. Maybe its useful to someone.

Wow. Actually it's useful to me now for something else. Nice to see my current design choice validated in numbers too.

[Kleinstein]

......
To be honest I've never used a simulator in my life. I generally "simulate" in solder, but you are right. With an expected load of 10M, any worthwhile series resistance will contribute significantly to a droopy output.

This is the first time I've ever posted a design for critique before committing to solder. Glad I did

The simulation with LTspice or Tina is a quite powerful tool and not that complicated anymore. The simulations are not perfect, but still quite accurate if parasitic components are included. Especially circuits like combining 2 or 3 OPs in a not so simple circuit are better simulated first.

Even with a 10 M load, the output resistor (e.g. 50 Ohms range to have an effect) can have an influence. It is relatively easy to avoid that error, by splitting AC and DC feedback: AC from before the resistor or from before the LT1010 and DC from behind the output resistor. This is pretty standard. The not so good alternative would be an inductor in parallel to the resistor.

[Cerebus]

Are you sure that the 4th pin on those 2N4117As is just the case, often the 4th pin on FETs is also substrate. Could ruin your day actively driving the substrate. Neither of the 2N4117 data sheets I have is explicit on the point, if I were you I'd want to get this confirmed or denied.

I might want to test that then. The interfet data sheet linked from the Mouser page I bought them from states "1-Source, 2-Drain, 3-Gate, 4- Case".
Never having looked at a JFet before and having 4 here on the desk, what would be a realistic way of measuring that without setting fire to a $15 FET?

Big resistor, say 1M, connect it to the suspected substrate. Ground the source, raise the suspected substrate (via the resistor, natch) to ~0.6V above ground and measure the current flow. If there is any, it's substrate, if there isn't it's just the case. On a 2N4117 it won't take much current to fry things, so don't omit that resistor.

Much appreciated. Used a 1M resistor. Pin 4 is connected to the case but there was absolutely no current between pin 4 and source. I double checked to make sure it was all good by swapping from the case to the gate, and got the expected Gate->Source current.

Excellent, so we've all learned something. I doubt that I'll ever shell out for metal cased x4117s (I have a stock of SOT-23 4117s I use for this kind of thing) but if I do, I now know definitively what that 4th pin does.

[MiDi]

If the FETs are too expensive one could consider low leakage diodes like BAV199. The typical leakage current is comparable, but not guarantied (tested). Changes are very good to be way lower than the OPs bias.

Or 1N3595, max 1nA @-125V and quite cheap