Fast settling PWM DAC

[MasterT]

deleted

[ch_scr]

I've implemented their similar circuit.
Put quite the effort with optical isolation for the PWM signal, star gnd and power, wima foil caps. There are still "blips" on the output 
The DMM reading is remarkably stable though. Driving it with PWM from the Rigol function gen for now.
Don't look too closely at the Vref section, those are 5 quad 10k resistor networks to get the "right" ratio, to precisely 10V, with slight padding.
Only wish I had put +-Vref on the input switch instead of +Vref&Gnd - think this could make a decent tool to sweep DMM input linearity then?
The zero volt out would be around 50% PWM then, where the DAC's linearity is highest.
Also no need to precisely trim Vref (like I did), rather have it above intended Vout min/max and reduce the PWM range slightly, avoiding the non-linear ends.
Having a precise Vref and measuring and correcting linearity digitally is possible as well when a "more linear" ref meter can be accessed.

Edit: Added a picture of the "patient" as well. Might have gone a bit over the top with the Vref/R network draft shields.
The wire jumpers just tie the Gnd plane static shield together. A bit over the top again, I guess.

[ch_scr]

I use a time constant slightly longer than F_pwm because the LTspice sim shows lower ripple for that case.
I use low F_pwm (100Hz) because it allows me to get 21 bit PWM resolution directly from FPGA (Tang nano). It's about the limit what I'm able to squeeze out of it.
Also 100Hz seems reasonable for something a DMM would have an easier time to suppress?
I built the +-10V version and measured it's linearity. Simpler gain resistor arrangement, ~10.55V Vref and digitally calibrated with PWM steps to +-10V.
It's good to not need the really needle sharp pulses for the max Vout and avoid lower linearity towards the ends. But it's a trade off since one leaves part of the resolution unused that way.
I attach alternating the uncorrected sweep and the correction function(s) fitted. I cal zero and both end points, then the correction constants are also individual for negative and positive sides.
I got it to +-3LSD linearity compared to "fake" Keithley 2100. There seems to be a curious "dip" in linearity at +-0.7V. It's getting into the weeds so close to the DMM resolution limit anyway.
Sweep steps are 100mV from 10V down to 100mV, then 10mV from 100mV down to 10mV, 1mV  from 10mV down to 1mV and 100uV from 1mV down to 100uV.
Hence the sweep graphs look wider around center. I wait 5 seconds for the DAC to settle and take the average of 3 10NPLC readings.

[Benta]

If you have access to "Art of Electronic, the X-Chapters", I strongly suggest you read section 4x.25.
They show a brilliant little circuit that either improves settling time by appr. a factor 8, or reduces ripple by a similar factor for the original settling time.

[ch_scr]

This uses a different idea, https://www.edn.com/fast-settling-synchronous-pwm-dac-filter-has-almost-no-ripple/.
The initial dac steps settle quite fast, but the integrators takes some time to reach final equilibrium.
I have added resistors R16 / R17 (see schematic in post above) to reduce spikes on the output (tried a lot in spice)
but they seem likely to be to blame for this. I will have to experiment a bit with the real circuit now, if they are actually needed / what the trade-off is.

[moffy]

If you have access to "Art of Electronic, the X-Chapters", I strongly suggest you read section 4x.25.
They show a brilliant little circuit that either improves settling time by appr. a factor 8, or reduces ripple by a similar factor for the original settling time.

Thanks for the reference, I was interested in the circuit which looked intriguing so I ran an LTSpice sim of it, quite impressive. But when I did a phase/gain plot of the filter, it reminded me of just a passive 2nd order filter with the same components, so I did a comparison, and the transient and phase gain plots were identical. The sim shown shows Va and Vb which are a perfect match and looks like a single trace because they perfectly overlay one another. I used the same values for the Rs and Cs as recommended in the book.

[Benta]

If you have access to "Art of Electronic, the X-Chapters", I strongly suggest you read section 4x.25.
They show a brilliant little circuit that either improves settling time by appr. a factor 8, or reduces ripple by a similar factor for the original settling time.

Thanks for the reference, I was interested in the circuit which looked intriguing so I ran an LTSpice sim of it, quite impressive. But when I did a phase/gain plot of the filter, it reminded me of just a passive 2nd order filter with the same components, so I did a comparison, and the transient and phase gain plots were identical. The sim shown shows Va and Vb which are a perfect match and looks like a single trace because they perfectly overlay one another. I used the same values for the Rs and Cs as recommended in the book.

Interesting. I never did a sim myself.
But that it converges to a 2nd-order LPF seems very plausible.
Thanks for trying.

[ch_scr]

I've tried to improve the settling, and while 470 for R16 seemed excessive, a test with 60 showed a strongly distorted non-linearity curve and the DAC was unwilling to settle around zero.
I made some trials with 120 for R16, but in the end incorporated a resistor in series with the switched capacitor like shown in the circuit in the first post (R21 in my schematic).
With R21=180 and R16=60 (to limit the current spikes of the opamp output) I got the un-corrected non-linearity shape basically like before.
I managed to hit +-35uV linearity with symmetric correction values with that arrangement. That is repeated runs, up or down, 1 or 2s settling for each DAC step (maximum step 0.1V).
The correction values now are almost the same as for the first tests with only R16=470 .
I think the slow settling could also be a dielectric absorption effect in the integration capacitor(s) - it seems to take longer to settle from -10V to +10V (or reverse) after having been in one state for a long time.

[MasterT]

Your circuits is stupid and I have no interest to discuss .
Why you don't create your own thread?  Otherway it's called thread hijacking

[dietert1]

Aren't the two circuits shown very similar and based on the same idea, a sample and hold filter? What is the difference?

Regards, Dieter

[MasterT]

Creativity is the difference between monkey and human, in all other senses they are very similar.
There is, of course, human-alike w/o creativity, would you think they are also human kind or "undefined" like AI?

[ch_scr]

@MasterT: I'm sorry, I had no intention to offend you. I didn't know a better way to do it / had some constraints I set myself.
I used e.g. these specific analog switches since I bought them as a possible upgrade for the Solartron 7150 forcing waveform switch (already at hand).
I'm also aware I could have used e.g. better/more modern OPA, but since I'm still exploring I wanted to see what was possible with these I had (recycled).
Some the component choices might look strange to someone who already knows what to optimize for?
Of some shortcomings with respect to the design choices I'm aware as well, e.g. too low modulator freq causing inevitable output blip.
Since I want to measure DMM input linearity, I don't care if there is a blip on it on the scope, as long as the 10NPLC reading is stable.
And I just yet reached the point to make a Vref with that stability.
Looking at the Solartron 7150 schematic again, I also just noticed I carelessly forgot the guard rings for the integrator input nodes...

[dietert1]

Creativity is the difference between monkey and human, in all other senses they are very similar.
There is, of course, human-alike w/o creativity, would you think they are also human kind or "undefined" like AI?

A strange statement, unless you were EDN author Stephen Woodward. Otherwise i'd say both of you tested the same circuit proposed by Stephen Woodward. I once tested his proposal for PWM ripple compensation and it worked.

https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/msg3567571/#msg3567571

Regards, Dieter

[MasterT]

I know for sure, that "composite amplifier" is my invention.
And word itself "composite" was taken out of Metallurgy vocabular...
And another countless number of inventions were stolen by human-alikes.

 The problem with parasitic business, is that new idea possessor / patent holder
is newer completely understand details of the inventions, that were re-flashed in
his piggy /oligoprenic brain. No he can ever improve original stolen design.
 
 So human-alike peoples manipulate i-networks, desperately trying to conduct "blind interrogations"
 to fill/ complete a gaps.
 And here is another issue, to complete a task they need a creativity in theirs DNA, that imbecile
 doesn't have in the first place.
 
"Circulus vitiosus".
 
As they say, Nolite mittere margaritas ante porcos.  Use Poison instead of "margaritas".
 
 

[ch_scr]

I am/was aware I lack understanding of this circuit, and am blind to it's inner workings. But the reason for that is... it's very hard to simulate.
The stupid changes I made, were made to make it work in LTspice. Then, when not getting further there, I decided to build one to see. Obviously build it "as simulated"...
I didn't have a suitable PWM generator at the time, so it got shelved and forgotten. Now 3 year later, better generator & simple FPGA capability at hand,
previous problems and details happily forgotten and inspired by your post; I did some updates to the surrounding circuit, but just left the not understood "core mystery part" alone.
I now tried simulating it in Qspice as well, and it needing different "simulation help" circuit elements (and turning off "fast math" in the settings as well), it's still quite temperamental.
But at least I could see a bit how what I added wasn't helping. Now removing the parts originally "added for simulation", output HF noise and switching blip did decrease tremendously 
I've attached the updated schematic and layout and a picture of the Rdson of the switches used, when running +-Vref instead of Gnd/+Vref the resistance symmetry should be good enough?

Edit: Surprising to me, the NL shape didn't change much from that though!

[Kleinstein]

The circuit shows the OP27 with 120 K at the input. This is not a good combination and rather noisy from the current noise. For a high resistance source suitable OP-amps are more OPA140 (and related cheaper ones), OPA205 or ADA4077 or maybe an AZ type like LTC2057 in some places if the resistance is not too high (e.g. 50 K).

 Because of the switch resistance one kind of wants high resistance, at least if very high linearity is wanted. The resistance at the DG419 is resonable symmetric and if needed one could add a resistor to trim. At least the PWM switch is only used with fixed ref. voltage - no need to match over a larger range.