Phase comparator and PLL, ringing and overshooting

[PCB.Wiz]

Today i found this german blog entry about the 4046: https://www.elektronik-kompendium.de/public/schaerer/pll4046.htm
The person claims that the input pin 14 doesn't work reliably with a digital input signal. He found that there is an input amplifier meant for signals with 1 or 2 V amplitude and with sharp edges. Strange.

Interesting notes.  I can believe the slew-rate issues, as he was trying to design at 50Hz, but the claims that proper CMOS drive has issues, is less convincing.   

The test done by driving outside the rails may be showing lateral current effects, and certainly analog CMOS does not like injected currents.
eg a vanilla 4051 can disturb analog signals, if an adjacent channel is clamping.

Maybe here, the biasing is disturbed enough, by ringing or overshoot. They spec for proper CMOS drive, so I cannot see that being a failure point.

It would be better to probe both Pin 2 and Pin 1, as pin 2 has more direct connection to the AC coupled amplifier. 

As a caution, maybe a design should ensure pin14 is 'clean and local' CMOS.

[Ken27]

Today i found this german blog entry about the 4046: https://www.elektronik-kompendium.de/public/schaerer/pll4046.htm
The person claims that the input pin 14 doesn't work reliably with a digital input signal. He found that there is an input amplifier meant for signals with 1 or 2 V amplitude and with sharp edges. Strange.

Regards, Dieter

Nice article! Yet I am not convinced too about the CMOS drive issues..

The 74HC works pretty well.

This is a video (converted to gif for size) of the phase lock at 10 kHz. It's real time (the animation is not faster than reality)

https://ibb.co/tBSNXRS

this is with cold warm-up for both GPS (once locked) and the VCOXCO .